Hi,
this simple patch adds regs required for implementing occlusion queries
support. I also changed R500_SU_REG_DEST to R300_* as it exists on R300 cards
too.
Maciej Cencora
From 47b6fab19665a823a89c90e4987e1a0b281f658b Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cenc...@gmail.com>
Date: Tue, 24 Mar 2009 01:48:50 +0100
Subject: [PATCH] drm/radeon: add regs required for occlusion queries support
Signed-off-by: Maciej Cencora <m.cenc...@gmail.com>
---
drivers/gpu/drm/radeon/r300_cmdbuf.c | 6 +++++-
drivers/gpu/drm/radeon/radeon_reg.h | 8 ++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index e093532..d907b71 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -205,6 +205,10 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
ADD_RANGE(R300_RE_CULL_CNTL, 1);
ADD_RANGE(0x42C0, 2);
+ ADD_RANGE(R300_SU_REG_DEST, 1);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
+ ADD_RANGE(RV530_FG_ZBREG_DEST, 1);
+ }
ADD_RANGE(R300_RS_CNTL_0, 2);
ADD_RANGE(0x43A4, 2);
@@ -234,6 +238,7 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(0x4F30, 2);
ADD_RANGE(0x4F44, 1);
ADD_RANGE(0x4F54, 1);
+ ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */
ADD_RANGE(R300_TX_FILTER_0, 16);
ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -251,7 +256,6 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
- ADD_RANGE(R500_SU_REG_DEST, 1);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
ADD_RANGE(R300_DST_PIPE_CONFIG, 1);
}
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 0edb592..b3b3d24 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -4086,8 +4086,6 @@
# define R300_ALPHA3_SHADING_GOURAUD (2 << 14)
#define R300_GA_OFFSET 0x4290
-#define R500_SU_REG_DEST 0x42c8
-
#define R300_VAP_CNTL_STATUS 0x2140
# define R300_PVS_BYPASS (1 << 8)
#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
@@ -4350,6 +4348,12 @@
# define R300_FACE_NEG (1 << 2)
#define R300_SU_DEPTH_SCALE 0x42c0
#define R300_SU_DEPTH_OFFSET 0x42c4
+#define R300_SU_REG_DEST 0x42c8
+#define RV530_FG_ZBREG_DEST 0x4be8
+
+#define R300_ZB_ZPASS_DATA 0x4f58
+#define R300_ZB_ZPASS_ADDR 0x4f5c
+
#define R300_RS_COUNT 0x4300
# define R300_RS_COUNT_IT_COUNT_SHIFT 0
--
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