Here's the pair of patches I've got to make A17-afflicted machines do tiling. I've created regression tests for swapping tiled objects and for pread on tiled objects, and I'm at 1/10 failures in intel-gpu-tools, or 0/10 if I disable BO reuse (appears to be a bug in fencing on objects getting reused as tiled after being linear). 3D performance is back to normal on my affected 945GM, and no_rast=true glxgears looks good.
I haven't written a regression test for tiled pwrite yet, is my only concern. ------------------------------------------------------------------------------ This SF.net email is sponsored by: High Quality Requirements in a Collaborative Environment. Download a free trial of Rational Requirements Composer Now! http://p.sf.net/sfu/www-ibm-com -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
