Dave Airlie skrev: > On Thu, Jun 25, 2009 at 10:01 PM, Jerome Glisse<gli...@freedesktop.org> wrote: > >> Hi, >> >> Thomas i attach a reworked page pool allocator based on Dave works, >> this one should be ok with ttm cache status tracking. It definitely >> helps on AGP system, now the bottleneck is in mesa vertex's dma >> allocation. >> >> > > My original version kept a list of wb pages as well, this proved to be > quite a useful > optimisation on my test systems when I implemented it, without it I > was spending ~20% > of my CPU in getting free pages, granted I always used WB pages on > PCIE/IGP systems. > > Another optimisation I made at the time was around the populate call, > (not sure if this > is what still happens): > > Allocate a 64K local BO for DMA object. > Write into the first 5 pages from userspace - get WB pages. > Bind to GART, swap those 5 pages to WC + flush. > Then populate the rest with WC pages from the list. > Granted I think allocating WC in the first place from the pool might > work just as well since most of the DMA buffers are write only. >
Yes, I think in the latter case the user-space driver should take care to specify WC from the beginning, when the BO is allocated. BTW is there any DMA buffer verification taking place on WC buffers on Radeon? > Dave. > /Thomas ------------------------------------------------------------------------------ -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
