Kernel driver is using magic numbers for some register access which makes
reading code harder. using prober defines and adding some missing once from
register documentations.
-----
I'm leaving for weekend trip where I don't have Internet connection so I
will continue working with this path in Sunday if there is some problems.
Also this doesn't address r100/200 magic numbers because I didn't have time
do it before leaving for trip. I tough it would be best to publish what I
have before leaving.
Pauli
From 52150fa4c54c8456a32148c369d837e68fd201c0 Mon Sep 17 00:00:00 2001
From: Pauli Nieminen <suok...@gmail.com>
Date: Fri, 4 Sep 2009 01:17:12 +0300
Subject: [PATCH] drm/radeon: Change some magic numbers to defines instead.
Kernel driver is using magic numbers for some register access which makes
reading code harder. using prober defines and adding some missing once from
register documentations.
Signed-off-by: Pauli Nieminen <suok...@gmail.com>
---
drivers/gpu/drm/radeon/r100.c | 5 +-
drivers/gpu/drm/radeon/r300.c | 245 ++++++++++++++++++-----------------
drivers/gpu/drm/radeon/r300_reg.h | 84 ++++++++++++-
drivers/gpu/drm/radeon/r420.c | 4 +-
drivers/gpu/drm/radeon/r520.c | 2 +-
drivers/gpu/drm/radeon/radeon_reg.h | 19 +++
drivers/gpu/drm/radeon/rv515.c | 4 +-
7 files changed, 237 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 639d5b2..3def3a9 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -346,8 +346,9 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
/* Who ever call radeon_fence_emit should call ring_lock and ask
* for enough space (today caller are ib schedule and buffer move) */
/* Wait until IDLE & CLEAN */
- radeon_ring_write(rdev, PACKET0(0x1720, 0));
- radeon_ring_write(rdev, (1 << 16) | (1 << 17));
+ radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+ radeon_ring_write(rdev, RADEON_WAIT_3D_IDLECLEAN
+ | RADEON_WAIT_2D_IDLECLEAN);
/* Emit fence sequence & fire IRQ */
radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
radeon_ring_write(rdev, fence->seq);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 482d6b2..23f4c06 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -123,7 +123,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
/* Clear error */
- WREG32_PCIE(0x18, 0);
+ WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
tmp |= RADEON_PCIE_TX_GART_EN;
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
@@ -254,18 +254,19 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
/* Who ever call radeon_fence_emit should call ring_lock and ask
* for enough space (today caller are ib schedule and buffer move) */
/* Write SC register so SC & US assert idle */
- radeon_ring_write(rdev, PACKET0(0x43E0, 0));
+ radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
radeon_ring_write(rdev, 0);
- radeon_ring_write(rdev, PACKET0(0x43E4, 0));
+ radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
radeon_ring_write(rdev, 0);
/* Flush 3D cache */
- radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
- radeon_ring_write(rdev, (2 << 0));
- radeon_ring_write(rdev, PACKET0(0x4F18, 0));
- radeon_ring_write(rdev, (1 << 0));
+ radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+ radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
+ radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+ radeon_ring_write(rdev, R300_ZC_FLUSH);
/* Wait until IDLE & CLEAN */
- radeon_ring_write(rdev, PACKET0(0x1720, 0));
- radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
+ radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+ radeon_ring_write(rdev, RADEON_WAIT_3D_IDLECLEAN
+ | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
/* Emit fence sequence & fire IRQ */
radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
radeon_ring_write(rdev, fence->seq);
@@ -290,7 +291,7 @@ int r300_copy_dma(struct radeon_device *rdev,
/* radeon pitch is /64 */
size = num_pages << PAGE_SHIFT;
- num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
+ num_loops = DIV_ROUND_UP(size, RADEON_CP_COMMAND_COUNT_MASK);
r = radeon_ring_lock(rdev, num_loops * 4 + 64);
if (r) {
DRM_ERROR("radeon: moving bo (%d).\n", r);
@@ -298,25 +299,29 @@ int r300_copy_dma(struct radeon_device *rdev,
}
/* Must wait for 2D idle & clean before DMA or hangs might happen */
radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
- radeon_ring_write(rdev, (1 << 16));
+ radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN);
+
for (i = 0; i < num_loops; i++) {
cur_size = size;
- if (cur_size > 0x1FFFFF) {
- cur_size = 0x1FFFFF;
- }
+ if (cur_size > RADEON_CP_COMMAND_COUNT_MASK)
+ cur_size = RADEON_CP_COMMAND_COUNT_MASK;
+
size -= cur_size;
- radeon_ring_write(rdev, PACKET0(0x720, 2));
+ radeon_ring_write(rdev, PACKET0(RADEON_CP_GUI_SRC_ADDR, 2));
radeon_ring_write(rdev, src_offset);
radeon_ring_write(rdev, dst_offset);
- radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
+ radeon_ring_write(rdev, cur_size
+ | RADEON_CP_COMMAND_EOL | RADEON_CP_COMMAND_INTDIS);
src_offset += cur_size;
dst_offset += cur_size;
}
+
radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
- if (fence) {
+
+ if (fence)
r = radeon_fence_emit(rdev, fence);
- }
+
radeon_ring_unlock_commit(rdev);
return r;
}
@@ -360,8 +365,8 @@ void r300_ring_start(struct radeon_device *rdev)
radeon_ring_write(rdev,
RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN);
- radeon_ring_write(rdev, PACKET0(0x170C, 0));
- radeon_ring_write(rdev, 1 << 31);
+ radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
+ radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
radeon_ring_write(rdev, 0);
radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
@@ -473,8 +478,8 @@ void r300_gpu_init(struct radeon_device *rdev)
"programming pipes. Bad things might happen.\n");
}
- tmp = RREG32(0x170C);
- WREG32(0x170C, tmp | (1 << 31));
+ tmp = RREG32(R300_DST_PIPE_CONFIG);
+ WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
WREG32(R300_RB2D_DSTCACHE_MODE,
R300_DC_AUTOFLUSH_ENABLE |
@@ -502,6 +507,7 @@ int r300_ga_reset(struct radeon_device *rdev)
for (i = 0; i < rdev->usec_timeout; i++) {
WREG32(RADEON_CP_CSQ_MODE, 0);
WREG32(RADEON_CP_CSQ_CNTL, 0);
+ /* reset GA, CP and VAP; What are the meaning of bits? */
WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
(void)RREG32(RADEON_RBBM_SOFT_RESET);
udelay(200);
@@ -509,25 +515,29 @@ int r300_ga_reset(struct radeon_device *rdev)
/* Wait to prevent race in RBBM_STATUS */
mdelay(1);
tmp = RREG32(RADEON_RBBM_STATUS);
- if (tmp & ((1 << 20) | (1 << 26))) {
- DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
+ if (tmp & (R300_RBBM_STATUS_VAP_BUSY
+ | R300_RBBM_STATUS_GA_BUSY)) {
+ DRM_ERROR("VAP & GA still busy (RBBM_STATUS=0x%08X)",
+ tmp);
/* GA still busy soft reset it */
- WREG32(0x429C, 0x200);
+ WREG32(R300_GA_SOFTRESET, R300_GA_SOFTRESET_DO_RESET);
WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- WREG32(0x43E0, 0);
- WREG32(0x43E4, 0);
- WREG32(0x24AC, 0);
+ WREG32(R300_RE_SCISSORS_TL, 0);
+ WREG32(R300_RE_SCISSORS_BR, 0);
+ WREG32(R300_VAP_VTX_END_OF_PKT, 0);
}
/* Wait to prevent race in RBBM_STATUS */
mdelay(1);
tmp = RREG32(RADEON_RBBM_STATUS);
- if (!(tmp & ((1 << 20) | (1 << 26)))) {
+ if (!(tmp & (R300_RBBM_STATUS_VAP_BUSY
+ | R300_RBBM_STATUS_GA_BUSY))) {
break;
}
}
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(RADEON_RBBM_STATUS);
- if (!(tmp & ((1 << 20) | (1 << 26)))) {
+ if (!(tmp & (R300_RBBM_STATUS_VAP_BUSY
+ | R300_RBBM_STATUS_GA_BUSY))) {
DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
tmp);
if (reinit_cp) {
@@ -555,17 +565,18 @@ int r300_gpu_reset(struct radeon_device *rdev)
r100_rb2d_reset(rdev);
}
/* reset GA */
- if (status & ((1 << 20) | (1 << 26))) {
+ if (status & (R300_RBBM_STATUS_VAP_BUSY
+ | R300_RBBM_STATUS_GA_BUSY))
r300_ga_reset(rdev);
- }
+
/* reset CP */
status = RREG32(RADEON_RBBM_STATUS);
- if (status & (1 << 16)) {
+ if (status & R300_RBBM_STATUS_CP_BUSY)
r100_cp_reset(rdev);
- }
+
/* Check if GPU is idle */
status = RREG32(RADEON_RBBM_STATUS);
- if (status & (1 << 31)) {
+ if (status & RADEON_RBBM_ACTIVE) {
DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
return -1;
}
@@ -1062,33 +1073,33 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].robj = reloc->robj;
break;
/* Tracked registers */
- case 0x2084:
+ case R300_VAP_VF_CNTL:
/* VAP_VF_CNTL */
track->vap_vf_cntl = ib_chunk->kdata[idx];
break;
- case 0x20B4:
+ case R300_VAP_VTX_SIZE:
/* VAP_VTX_SIZE */
track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
break;
- case 0x2134:
+ case R300_VAP_VF_MAX_VTX_INDX:
/* VAP_VF_MAX_VTX_INDX */
track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
break;
- case 0x43E4:
+ case R300_RE_SCISSORS_BR:
/* SC_SCISSOR1 */
track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
if (p->rdev->family < CHIP_RV515) {
track->maxy -= 1440;
}
break;
- case 0x4E00:
+ case R300_RB3D_CCTL:
/* RB3D_CCTL */
track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
break;
- case 0x4E38:
- case 0x4E3C:
- case 0x4E40:
- case 0x4E44:
+ case R300_RB3D_COLORPITCH0:
+ case R300_RB3D_COLORPITCH1:
+ case R300_RB3D_COLORPITCH2:
+ case R300_RB3D_COLORPITCH3:
/* RB3D_COLORPITCH0 */
/* RB3D_COLORPITCH1 */
/* RB3D_COLORPITCH2 */
@@ -1139,7 +1150,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
return -EINVAL;
}
break;
- case 0x4F00:
+ case R300_ZB_CNTL:
/* ZB_CNTL */
if (ib_chunk->kdata[idx] & 2) {
track->z_enabled = true;
@@ -1147,7 +1158,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->z_enabled = false;
}
break;
- case 0x4F10:
+ case R300_ZB_FORMAT:
/* ZB_FORMAT */
switch ((ib_chunk->kdata[idx] & 0xF)) {
case 0:
@@ -1163,7 +1174,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
return -EINVAL;
}
break;
- case 0x4F24:
+ case R300_ZB_DEPTHPITCH:
/* ZB_DEPTHPITCH */
r = r100_cs_packet_next_reloc(p, &reloc);
if (r) {
@@ -1184,7 +1195,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
break;
- case 0x4104:
+ case R300_TX_ENABLE:
for (i = 0; i < 16; i++) {
bool enabled;
@@ -1192,24 +1203,24 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].enabled = enabled;
}
break;
- case 0x44C0:
- case 0x44C4:
- case 0x44C8:
- case 0x44CC:
- case 0x44D0:
- case 0x44D4:
- case 0x44D8:
- case 0x44DC:
- case 0x44E0:
- case 0x44E4:
- case 0x44E8:
- case 0x44EC:
- case 0x44F0:
- case 0x44F4:
- case 0x44F8:
- case 0x44FC:
+ case R300_TX_FORMAT_0:
+ case R300_TX_FORMAT_1:
+ case R300_TX_FORMAT_2:
+ case R300_TX_FORMAT_3:
+ case R300_TX_FORMAT_4:
+ case R300_TX_FORMAT_5:
+ case R300_TX_FORMAT_6:
+ case R300_TX_FORMAT_7:
+ case R300_TX_FORMAT_8:
+ case R300_TX_FORMAT_9:
+ case R300_TX_FORMAT_10:
+ case R300_TX_FORMAT_11:
+ case R300_TX_FORMAT_12:
+ case R300_TX_FORMAT_13:
+ case R300_TX_FORMAT_14:
+ case R300_TX_FORMAT_15:
/* TX_FORMAT1_[0-15] */
- i = (reg - 0x44C0) >> 2;
+ i = (reg - R300_TX_FORMAT_0) >> 2;
tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
track->textures[i].tex_coord_type = tmp;
switch ((ib_chunk->kdata[idx] & 0x1F)) {
@@ -1258,24 +1269,24 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
break;
}
break;
- case 0x4400:
- case 0x4404:
- case 0x4408:
- case 0x440C:
- case 0x4410:
- case 0x4414:
- case 0x4418:
- case 0x441C:
- case 0x4420:
- case 0x4424:
- case 0x4428:
- case 0x442C:
- case 0x4430:
- case 0x4434:
- case 0x4438:
- case 0x443C:
+ case R300_TX_FILTER_0:
+ case R300_TX_FILTER_1:
+ case R300_TX_FILTER_2:
+ case R300_TX_FILTER_3:
+ case R300_TX_FILTER_4:
+ case R300_TX_FILTER_5:
+ case R300_TX_FILTER_6:
+ case R300_TX_FILTER_7:
+ case R300_TX_FILTER_8:
+ case R300_TX_FILTER_9:
+ case R300_TX_FILTER_10:
+ case R300_TX_FILTER_11:
+ case R300_TX_FILTER_12:
+ case R300_TX_FILTER_13:
+ case R300_TX_FILTER_14:
+ case R300_TX_FILTER_15:
/* TX_FILTER0_[0-15] */
- i = (reg - 0x4400) >> 2;
+ i = (reg - R300_TX_FILTER_0) >> 2;
tmp = ib_chunk->kdata[idx] & 0x7;;
if (tmp == 2 || tmp == 4 || tmp == 6) {
track->textures[i].roundup_w = false;
@@ -1285,24 +1296,24 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].roundup_h = false;
}
break;
- case 0x4500:
- case 0x4504:
- case 0x4508:
- case 0x450C:
- case 0x4510:
- case 0x4514:
- case 0x4518:
- case 0x451C:
- case 0x4520:
- case 0x4524:
- case 0x4528:
- case 0x452C:
- case 0x4530:
- case 0x4534:
- case 0x4538:
- case 0x453C:
+ case R300_TX_PITCH_0:
+ case R300_TX_PITCH_1:
+ case R300_TX_PITCH_2:
+ case R300_TX_PITCH_3:
+ case R300_TX_PITCH_4:
+ case R300_TX_PITCH_5:
+ case R300_TX_PITCH_6:
+ case R300_TX_PITCH_7:
+ case R300_TX_PITCH_8:
+ case R300_TX_PITCH_9:
+ case R300_TX_PITCH_10:
+ case R300_TX_PITCH_11:
+ case R300_TX_PITCH_12:
+ case R300_TX_PITCH_13:
+ case R300_TX_PITCH_14:
+ case R300_TX_PITCH_15:
/* TX_FORMAT2_[0-15] */
- i = (reg - 0x4500) >> 2;
+ i = (reg - R300_TX_PITCH_0) >> 2;
tmp = ib_chunk->kdata[idx] & 0x3FFF;
track->textures[i].pitch = tmp + 1;
if (p->rdev->family >= CHIP_RV515) {
@@ -1312,24 +1323,24 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].height_11 = tmp;
}
break;
- case 0x4480:
- case 0x4484:
- case 0x4488:
- case 0x448C:
- case 0x4490:
- case 0x4494:
- case 0x4498:
- case 0x449C:
- case 0x44A0:
- case 0x44A4:
- case 0x44A8:
- case 0x44AC:
- case 0x44B0:
- case 0x44B4:
- case 0x44B8:
- case 0x44BC:
+ case R300_TX_SIZE_0:
+ case R300_TX_SIZE_1:
+ case R300_TX_SIZE_2:
+ case R300_TX_SIZE_3:
+ case R300_TX_SIZE_4:
+ case R300_TX_SIZE_5:
+ case R300_TX_SIZE_6:
+ case R300_TX_SIZE_7:
+ case R300_TX_SIZE_8:
+ case R300_TX_SIZE_9:
+ case R300_TX_SIZE_10:
+ case R300_TX_SIZE_11:
+ case R300_TX_SIZE_12:
+ case R300_TX_SIZE_13:
+ case R300_TX_SIZE_14:
+ case R300_TX_SIZE_15:
/* TX_FORMAT0_[0-15] */
- i = (reg - 0x4480) >> 2;
+ i = (reg - R300_TX_SIZE_0) >> 2;
tmp = ib_chunk->kdata[idx] & 0x7FF;
track->textures[i].width = tmp + 1;
tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
@@ -1351,7 +1362,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
}
ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
break;
- case 0x4be8:
+ case RV530_FG_ZBREG_DEST:
/* valid register only on RV530 */
if (p->rdev->family == CHIP_RV530)
break;
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef..5743e4d 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -31,6 +31,13 @@
#define R300_SURF_TILE_MICRO (2<<16)
#define R300_SURF_TILE_BOTH (3<<16)
+/*#define RADEON_RBBM_STATUS*/
+# define R300_RBBM_STATUS_CP_BUSY (1 << 16)
+# define R300_RBBM_STATUS_VAP_BUSY (1 << 20)
+# define R300_RBBM_STATUS_GA_BUSY (1 << 26)
+
+#define R300_GA_SOFTRESET 0x429C
+# define R300_GA_SOFTRESET_DO_RESET 0x200
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
@@ -147,7 +154,7 @@
/* BEGIN: Vertex data assembly - lots of uncertainties */
/* gap */
-
+#define R300_VAP_VF_MAX_VTX_INDX 0x2134
#define R300_VAP_CNTL_STATUS 0x2140
# define R300_VC_NO_SWAP (0 << 0)
# define R300_VC_16BIT_SWAP (1 << 0)
@@ -364,6 +371,7 @@
/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
* immediate vertices
*/
+#define R300_VAP_VTX_SIZE 0x20B4
#define R300_VAP_VTX_COLOR_R 0x2464
#define R300_VAP_VTX_COLOR_G 0x2468
#define R300_VAP_VTX_COLOR_B 0x246C
@@ -796,6 +804,21 @@
* register TX_OFFSET_0 + (4*N)
*/
#define R300_TX_FILTER_0 0x4400
+#define R300_TX_FILTER_1 0x4404
+#define R300_TX_FILTER_2 0x4408
+#define R300_TX_FILTER_3 0x440C
+#define R300_TX_FILTER_4 0x4410
+#define R300_TX_FILTER_5 0x4414
+#define R300_TX_FILTER_6 0x4418
+#define R300_TX_FILTER_7 0x441C
+#define R300_TX_FILTER_8 0x4420
+#define R300_TX_FILTER_9 0x4424
+#define R300_TX_FILTER_10 0x4428
+#define R300_TX_FILTER_11 0x442C
+#define R300_TX_FILTER_12 0x4430
+#define R300_TX_FILTER_13 0x4434
+#define R300_TX_FILTER_14 0x4438
+#define R300_TX_FILTER_15 0x443C
# define R300_TX_REPEAT 0
# define R300_TX_MIRRORED 1
# define R300_TX_CLAMP 4
@@ -851,6 +874,21 @@
# define R300_ANISO_THRESHOLD_MASK (7<<17)
#define R300_TX_SIZE_0 0x4480
+#define R300_TX_SIZE_1 0x4484
+#define R300_TX_SIZE_2 0x4488
+#define R300_TX_SIZE_3 0x448C
+#define R300_TX_SIZE_4 0x4490
+#define R300_TX_SIZE_5 0x4494
+#define R300_TX_SIZE_6 0x4498
+#define R300_TX_SIZE_7 0x449C
+#define R300_TX_SIZE_8 0x44A0
+#define R300_TX_SIZE_9 0x44A4
+#define R300_TX_SIZE_10 0x44A8
+#define R300_TX_SIZE_11 0x44AC
+#define R300_TX_SIZE_12 0x44B0
+#define R300_TX_SIZE_13 0x44B4
+#define R300_TX_SIZE_14 0x44B8
+#define R300_TX_SIZE_15 0x44BC
# define R300_TX_WIDTHMASK_SHIFT 0
# define R300_TX_WIDTHMASK_MASK (2047 << 0)
# define R300_TX_HEIGHTMASK_SHIFT 11
@@ -861,6 +899,21 @@
# define R300_TX_SIZE_PROJECTED (1<<30)
# define R300_TX_SIZE_TXPITCH_EN (1<<31)
#define R300_TX_FORMAT_0 0x44C0
+#define R300_TX_FORMAT_1 0x44C4
+#define R300_TX_FORMAT_2 0x44C8
+#define R300_TX_FORMAT_3 0x44CC
+#define R300_TX_FORMAT_4 0x44D0
+#define R300_TX_FORMAT_5 0x44D4
+#define R300_TX_FORMAT_6 0x44D8
+#define R300_TX_FORMAT_7 0x44DC
+#define R300_TX_FORMAT_8 0x44E0
+#define R300_TX_FORMAT_9 0x44E4
+#define R300_TX_FORMAT_10 0x44E8
+#define R300_TX_FORMAT_11 0x44EC
+#define R300_TX_FORMAT_12 0x44F0
+#define R300_TX_FORMAT_13 0x44F4
+#define R300_TX_FORMAT_14 0x44F8
+#define R300_TX_FORMAT_15 0x44FC
/* The interpretation of the format word by Wladimir van der Laan */
/* The X, Y, Z and W refer to the layout of the components.
They are given meanings as R, G, B and Alpha by the swizzle
@@ -942,7 +995,22 @@
# define R300_TX_FORMAT_YUV_MODE 0x00800000
-#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
+#define R300_TX_PITCH_0 0x4500
+#define R300_TX_PITCH_1 0x4504
+#define R300_TX_PITCH_2 0x4508
+#define R300_TX_PITCH_3 0x450C
+#define R300_TX_PITCH_4 0x4510
+#define R300_TX_PITCH_5 0x4514
+#define R300_TX_PITCH_6 0x4518
+#define R300_TX_PITCH_7 0x451C
+#define R300_TX_PITCH_8 0x4520
+#define R300_TX_PITCH_9 0x4524
+#define R300_TX_PITCH_10 0x4528
+#define R300_TX_PITCH_11 0x452C
+#define R300_TX_PITCH_12 0x4530
+#define R300_TX_PITCH_13 0x4534
+#define R300_TX_PITCH_14 0x4538
+#define R300_TX_PITCH_15 0x453C
#define R300_TX_OFFSET_0 0x4540
/* BEGIN: Guess from R200 */
# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
@@ -1300,6 +1368,18 @@
* function (both registers are always set up completely in any case)
* - Most blend flags are simply copied from R200 and not tested yet
*/
+#define R300_RB3D_CCTL 0x4E00
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_1 (0 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_2 (1 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_3 (2 << 5)
+# define R300_RB3D_CCTL_NUM_MULTIWRITES_4 (3 << 5)
+# define R300_RB3D_CCTL_MULTIWRITES_MASK (3 << 5)
+# define R300_RB3D_CCTL_CLRCMP_FLIPE (1 << 7)
+# define R300_RB3D_CCTL_AA_COMPRESSION (1 << 9)
+# define R300_RB3D_CCTL_CMASK (1 << 10)
+# define R300_RB3D_CCTL_IND_CLR_CHA_MASK (1 << 12)
+# define R300_RB3D_CCTL_WRITE_COMPRESSION (1 << 13)
+# define R300_RB3D_CCTL_IND_CLRFMT (1 << 14)
#define R300_RB3D_CBLEND 0x4E04
#define R300_RB3D_ABLEND 0x4E08
/* the following only appear in CBLEND */
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index dea497a..2559acc 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -153,8 +153,8 @@ void r420_pipes_init(struct radeon_device *rdev)
"programming pipes. Bad things might happen.\n");
}
- tmp = RREG32(0x170C);
- WREG32(0x170C, tmp | (1 << 31));
+ tmp = RREG32(R300_DST_PIPE_CONFIG);
+ WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
WREG32(R300_RB2D_DSTCACHE_MODE,
RREG32(R300_RB2D_DSTCACHE_MODE) |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 09fb0b6..12173e9 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -182,7 +182,7 @@ void r520_gpu_init(struct radeon_device *rdev)
}
r420_pipes_init(rdev);
gb_pipe_select = RREG32(0x402C);
- tmp = RREG32(0x170C);
+ tmp = RREG32(R300_DST_PIPE_CONFIG);
pipe_select_current = (tmp >> 2) & 3;
tmp = (1 << pipe_select_current) |
(((gb_pipe_select >> 8) & 0xF) << 4);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 5a098f3..f31f3d7 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3197,6 +3197,25 @@
#define RADEON_CP_RB_WPTR 0x0714
#define RADEON_CP_RB_RPTR_WR 0x071c
+#define RADEON_CP_GUI_SRC_ADDR 0x0720
+#define RADEON_CP_GUI_DST_ADDR 0x0724
+#define RADEON_CP_GUI_COMMAND 0x0728
+# define RADEON_CP_COMMAND_COUNT_MASK (0x1FFFFF)
+# define RADEON_CP_COMMAND_SRC_SWAP_16 (1 << 22)
+# define RADEON_CP_COMMAND_SRC_SWAP_32 (1 << 23)
+# define RADEON_CP_COMMAND_DST_SWAP_16 (1 << 24)
+# define RADEON_CP_COMMAND_DST_SWAP_32 (1 << 25)
+# define RADEON_CP_COMMAND_SAS (1 << 26) /* address space */
+# define RADEON_CP_COMMAND_DAS (1 << 27) /* address space */
+# define RADEON_CP_COMMAND_SAIC (1 << 28) /* increment address */
+# define RADEON_CP_COMMAND_DAIC (1 << 29) /* increment address */
+# define RADEON_CP_COMMAND_INTDIS (1 << 30) /* irq disable */
+# define RADEON_CP_COMMAND_EOL (1 << 31)
+/* Positioned here for easy of reference for command format */
+#define RADEON_CP_VID_SRC_ADDR 0x07c4
+#define RADEON_CP_VID_DST_ADDR 0x07c8
+#define RADEON_CP_VID_COMMAND 0x07cc
+
#define RADEON_CP_IB_BASE 0x0738
#define RADEON_CP_IB_BUFSZ 0x073c
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 60a194f..c37e1b1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -279,8 +279,8 @@ int rv515_ga_reset(struct radeon_device *rdev)
/* GA still busy soft reset it */
WREG32(0x429C, 0x200);
WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
- WREG32(0x43E0, 0);
- WREG32(0x43E4, 0);
+ WREG32(R300_RE_SCISSORS_TL, 0);
+ WREG32(R300_RE_SCISSORS_BR, 0);
WREG32(0x24AC, 0);
}
/* Wait to prevent race in RBBM_STATUS */
--
1.6.3.3
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