On Sun, Nov 22, 2009 at 9:01 PM, Dave Airlie <airl...@gmail.com> wrote:
> From: Dave Airlie <airl...@redhat.com>
>
> rendercheck under kms on r600s was failing due to HDP flushing not happening.
>
> This adds HDP flushing to the object wait function for r100->r700 families.
>
> rendercheck passes basic tests on r600 with this change.
>
> Signed-off-by: Dave Airlie <airl...@redhat.com>
Acked-by: Alex Deucher <alexdeuc...@gmail.com>
> ---
> drivers/gpu/drm/radeon/r100.c | 8 ++++++++
> drivers/gpu/drm/radeon/r600.c | 4 ++++
> drivers/gpu/drm/radeon/r600d.h | 1 +
> drivers/gpu/drm/radeon/radeon.h | 2 ++
> drivers/gpu/drm/radeon/radeon_asic.h | 12 ++++++++++++
> drivers/gpu/drm/radeon/radeon_object.c | 1 +
> 6 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index f0f2fbe..677fd72 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -1589,6 +1589,14 @@ void r100_gpu_init(struct radeon_device *rdev)
> r100_hdp_reset(rdev);
> }
>
> +void r100_hdp_flush(struct radeon_device *rdev)
> +{
> + u32 tmp;
> + tmp = RREG32(RADEON_HOST_PATH_CNTL);
> + tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
> + WREG32(RADEON_HOST_PATH_CNTL, tmp);
> +}
> +
> void r100_hdp_reset(struct radeon_device *rdev)
> {
> uint32_t tmp;
> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
> index 8d6bc12..ce421b6 100644
> --- a/drivers/gpu/drm/radeon/r600.c
> +++ b/drivers/gpu/drm/radeon/r600.c
> @@ -1101,6 +1101,10 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32
> reg, u32 v)
> (void)RREG32(PCIE_PORT_DATA);
> }
>
> +void r600_hdp_flush(struct radeon_device *rdev)
> +{
> + WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
> +}
>
> /*
> * CP & Ring
> diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
> index b99f45d..f33433d 100644
> --- a/drivers/gpu/drm/radeon/r600d.h
> +++ b/drivers/gpu/drm/radeon/r600d.h
> @@ -673,4 +673,5 @@
> #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) <<
> 16)
> #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) <<
> 17)
>
> +#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
> #endif
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 27c8b38..9783220 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -638,6 +638,7 @@ struct radeon_asic {
> uint32_t offset, uint32_t obj_size);
> int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
> void (*bandwidth_update)(struct radeon_device *rdev);
> + void (*hdp_flush)(struct radeon_device *rdev);
> };
>
> /*
> @@ -969,6 +970,7 @@ static inline void radeon_ring_write(struct radeon_device
> *rdev, uint32_t v)
> #define radeon_set_surface_reg(rdev, r, f, p, o, s)
> ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
> #define radeon_clear_surface_reg(rdev, r)
> ((rdev)->asic->clear_surface_reg((rdev), (r)))
> #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
> +#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
>
> /* Common functions */
> extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
> b/drivers/gpu/drm/radeon/radeon_asic.h
> index 94991ed..c84a15a 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -75,6 +75,7 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int
> reg);
> void r100_bandwidth_update(struct radeon_device *rdev);
> void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
> int r100_ring_test(struct radeon_device *rdev);
> +void r100_hdp_flush(struct radeon_device *rdev);
>
> static struct radeon_asic r100_asic = {
> .init = &r100_init,
> @@ -105,6 +106,7 @@ static struct radeon_asic r100_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &r100_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -159,6 +161,7 @@ static struct radeon_asic r300_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &r100_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
> /*
> @@ -197,6 +200,7 @@ static struct radeon_asic r420_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &r100_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -240,6 +244,7 @@ static struct radeon_asic rs400_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &r100_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -285,6 +290,7 @@ static struct radeon_asic rs600_asic = {
> .set_pcie_lanes = NULL,
> .set_clock_gating = &radeon_atom_set_clock_gating,
> .bandwidth_update = &rs600_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -327,6 +333,7 @@ static struct radeon_asic rs690_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &rs690_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -373,6 +380,7 @@ static struct radeon_asic rv515_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &rv515_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
>
> @@ -410,6 +418,7 @@ static struct radeon_asic r520_asic = {
> .set_surface_reg = r100_set_surface_reg,
> .clear_surface_reg = r100_clear_surface_reg,
> .bandwidth_update = &rv515_bandwidth_update,
> + .hdp_flush = &r100_hdp_flush,
> };
>
> /*
> @@ -445,6 +454,7 @@ int r600_ring_test(struct radeon_device *rdev);
> int r600_copy_blit(struct radeon_device *rdev,
> uint64_t src_offset, uint64_t dst_offset,
> unsigned num_pages, struct radeon_fence *fence);
> +void r600_hdp_flush(struct radeon_device *rdev);
>
> static struct radeon_asic r600_asic = {
> .init = &r600_init,
> @@ -473,6 +483,7 @@ static struct radeon_asic r600_asic = {
> .set_surface_reg = r600_set_surface_reg,
> .clear_surface_reg = r600_clear_surface_reg,
> .bandwidth_update = &rv515_bandwidth_update,
> + .hdp_flush = &r600_hdp_flush,
> };
>
> /*
> @@ -511,6 +522,7 @@ static struct radeon_asic rv770_asic = {
> .set_surface_reg = r600_set_surface_reg,
> .clear_surface_reg = r600_clear_surface_reg,
> .bandwidth_update = &rv515_bandwidth_update,
> + .hdp_flush = &r600_hdp_flush,
> };
>
> #endif
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c
> b/drivers/gpu/drm/radeon/radeon_object.c
> index 1f056da..98835f5 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -315,6 +315,7 @@ int radeon_object_wait(struct radeon_object *robj)
> }
> spin_unlock(&robj->tobj.lock);
> radeon_object_unreserve(robj);
> + radeon_hdp_flush(robj->rdev);
> return r;
> }
>
> --
> 1.6.5.2
>
>
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