Hi,
I'd like to propose two patches for kernel DRM.
Currently the R300 CS checker doesn't allow rendering with no color
buffer set. This is needed for depth-only rendering which is required
for rendering into depth textures to generate shadow maps. The first
attached patch removes this restriction by skipping checking the
colorbuffer if both ZB_BW_CNTL.FAST_FILL and
RB3D_BLENDCNTL.READ_ENABLE are disabled, and RB3D_COLOR_CHANNEL_MASK
is 0. When these bits are set, the hardware won't touch the
colorbuffer at all.
The second attached patch adds support for the 3DC texture compression
(formats ATI1N and ATI2N). The former has 64 bits per 4x4 pixel block
(same as DXT1) and is available on R4xx and up, and the latter has 128
bits per 4x4 pixel block (same as DXT3/5) and is available on R5xx.
This functionality can be exposed in OpenGL by
GL_EXT_texture_compression_latc and GL_ARB_texture_compression_rgtc,
which is part of OpenGL 3.0 and will most probably be implemented in
Mesa in future.
Frankly ATI1N can already be used as it occupies the same format bits
as TX_FMT_3_3_2 with the addition that TX_FORMAT2_n.TXFORMAT_MSB must
be set. The CS parser doesn't read the TXFORMAT_MSB bit at all, so it
always interprets the format as 3_3_2. If the MSB bit is set with the
second patch, the CS parser interprets any format as ATI1N, because
the other extended formats won't be used anyway as they are not
exposed by any graphics API. Let me know if you agree with this
behavior.
Please review.
Best regards
Marek Olšák
From 386484e581cf4df96e3a62318103bcaa610bb238 Mon Sep 17 00:00:00 2001
From: =?utf-8?q?Marek=20Ol=C5=A1=C3=A1k?= <mar...@gmail.com>
Date: Thu, 17 Dec 2009 06:02:28 +0100
Subject: [PATCH 1/2] drm/radeon/kms: allow rendering while no colorbuffer is set on r300
Because hardware cannot disable all colorbuffers directly to do depth-only
rendering, a user should:
- disable reading from a colorbuffer in blending
- disable fastfill
- set the color channel mask to 0 to prevent writing to a colorbuffer
---
drivers/gpu/drm/radeon/r100.c | 4 ++++
drivers/gpu/drm/radeon/r100_track.h | 4 +++-
drivers/gpu/drm/radeon/r300.c | 12 ++++++++++++
3 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 84e5df7..7172746 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2881,6 +2881,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
for (i = 0; i < track->num_cb; i++) {
if (track->cb[i].robj == NULL) {
+ if (!(track->fastfill || track->color_channel_mask ||
+ track->blend_read_enable)) {
+ continue;
+ }
DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 7188c37..b27a699 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -67,13 +67,15 @@ struct r100_cs_track {
unsigned immd_dwords;
unsigned num_arrays;
unsigned max_indx;
+ unsigned color_channel_mask;
struct r100_cs_track_array arrays[11];
struct r100_cs_track_cb cb[R300_MAX_CB];
struct r100_cs_track_cb zb;
struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
bool z_enabled;
bool separate_cube;
-
+ bool fastfill;
+ bool blend_read_enable;
};
int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2..6a5d117 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -992,6 +992,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
}
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
break;
+ case 0x4e0c:
+ /* RB3D_COLOR_CHANNEL_MASK */
+ track->color_channel_mask = idx_value;
+ break;
+ case 0x4d1c:
+ /* ZB_BW_CNTL */
+ track->fastfill = !!(idx_value & (1 << 2));
+ break;
+ case 0x4e04:
+ /* RB3D_BLENDCNTL */
+ track->blend_read_enable = !!(idx_value & (1 << 2));
+ break;
case 0x4be8:
/* valid register only on RV530 */
if (p->rdev->family == CHIP_RV530)
--
1.6.3.3
From e0d65186af2fbd6a73b3d4968347aee9e884f758 Mon Sep 17 00:00:00 2001
From: =?utf-8?q?Marek=20Ol=C5=A1=C3=A1k?= <mar...@gmail.com>
Date: Sat, 19 Dec 2009 00:23:00 +0100
Subject: [PATCH 2/2] drm/radeom/kms: add 3DC compression support
There are 2 formats:
ATI1N: 64 bits per 4x4 block, one-channel format
ATI2N: 128 bits per 4x4 block, two-channel format
---
drivers/gpu/drm/radeon/r300.c | 18 ++++++++++++++++++
drivers/gpu/drm/radeon/r300_reg.h | 1 +
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 6a5d117..3f2cc9e 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -887,6 +887,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].cpp = 1;
track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
break;
+ case R300_TX_FORMAT_ATI2N:
+ if (p->rdev->family < CHIP_R420) {
+ DRM_ERROR("Invalid texture format %u\n",
+ (idx_value & 0x1F));
+ return -EINVAL;
+ }
+ /* The same rules apply as for DXT3/5. */
+ /* Pass through. */
case R300_TX_FORMAT_DXT3:
case R300_TX_FORMAT_DXT5:
track->textures[i].cpp = 1;
@@ -951,6 +959,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
track->textures[i].width_11 = tmp;
tmp = ((idx_value >> 16) & 1) << 11;
track->textures[i].height_11 = tmp;
+
+ /* ATI1N */
+ if (idx_value & (1 << 14)) {
+ /* The same rules apply as for DXT1. */
+ track->textures[i].compress_format =
+ R100_TRACK_COMP_DXT1;
+ }
+ } else if (idx_value & (1 << 14)) {
+ DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
+ return -EINVAL;
}
break;
case 0x4480:
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef..1735a2b 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -900,6 +900,7 @@
# define R300_TX_FORMAT_FL_I32 0x1B
# define R300_TX_FORMAT_FL_I32A32 0x1C
# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
+# define R300_TX_FORMAT_ATI2N 0x1F
/* alpha modes, convenience mostly */
/* if you have alpha, pick constant appropriate to the
number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
--
1.6.3.3
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