>From e77f2fecc263ab237e56a897a67eee7574f9a2fb Mon Sep 17 00:00:00 2001 From: Alex Deucher <alexdeuc...@gmail.com> Date: Tue, 5 Jan 2010 17:27:33 -0500 Subject: [PATCH] drm/radeon/kms: use REG8 for HDP flush on r1xx-r5xx
Avoid touching bit 23 of HOST_PATH_CNTL as this can
cause hangs on some systems. Only read/write the
top 8 bits of HOST_PATH_CNTL.
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
---
drivers/gpu/drm/radeon/r100.c | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 6b8d9ad..3b39602 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1719,10 +1719,13 @@ void r100_gpu_init(struct radeon_device *rdev)
void r100_hdp_flush(struct radeon_device *rdev)
{
- u32 tmp;
- tmp = RREG32(RADEON_HOST_PATH_CNTL);
- tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
- WREG32(RADEON_HOST_PATH_CNTL, tmp);
+ u8 tmp;
+ /* read/write only the top 8 bits of HOST_PATH_CNTL as touching
+ * bit 23 can be problematic on some chips
+ */
+ tmp = RREG8(RADEON_HOST_PATH_CNTL + 3);
+ tmp |= (1 << 3); /* RADEON_HDP_READ_BUFFER_INVALIDATE */
+ WREG8(RADEON_HOST_PATH_CNTL + 3, tmp);
}
void r100_hdp_reset(struct radeon_device *rdev)
--
1.5.6.3
0001-drm-radeon-kms-use-REG8-for-HDP-flush-on-r1xx-r5xx.patch
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