On Fri, Feb 12, 2010 at 3:55 AM, Pauli Nieminen <suok...@gmail.com> wrote:
> Setting global asic structure to point to different function
> would cause problem in system where is multiple r300 cards
> with different bus type.
This contains a typo which I fixed locally please make sure it
compiles before sending to me ;-)
hint: rv370_pci_set_gart_flush
Dave.
>
> r300_asic_pcie is just copy from r300_asic with gart tlb
> functions replaced with pcie versions.
>
> Signed-off-by: Pauli Nieminen <suok...@gmail.com>
> ---
> drivers/gpu/drm/radeon/radeon_asic.h | 38
> ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/radeon/radeon_device.c | 9 +++----
> 2 files changed, 42 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
> b/drivers/gpu/drm/radeon/radeon_asic.h
> index 0971e7e..af18ffe 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -221,6 +221,44 @@ static struct radeon_asic r300_asic = {
> .ioctl_wait_idle = NULL,
> };
>
> +
> +static struct radeon_asic r300_asic_pcie = {
> + .init = &r300_init,
> + .fini = &r300_fini,
> + .suspend = &r300_suspend,
> + .resume = &r300_resume,
> + .vga_set_state = &r100_vga_set_state,
> + .gpu_reset = &r300_gpu_reset,
> + .gart_tlb_flush = &rv370_pci_gart_tlb_flush,
> + .gart_set_page = &rv370_pci_gart_set_page,
> + .cp_commit = &r100_cp_commit,
> + .ring_start = &r300_ring_start,
> + .ring_test = &r100_ring_test,
> + .ring_ib_execute = &r100_ring_ib_execute,
> + .irq_set = &r100_irq_set,
> + .irq_process = &r100_irq_process,
> + .get_vblank_counter = &r100_get_vblank_counter,
> + .fence_ring_emit = &r300_fence_ring_emit,
> + .cs_parse = &r300_cs_parse,
> + .copy_blit = &r100_copy_blit,
> + .copy_dma = &r200_copy_dma,
> + .copy = &r100_copy_blit,
> + .get_engine_clock = &radeon_legacy_get_engine_clock,
> + .set_engine_clock = &radeon_legacy_set_engine_clock,
> + .get_memory_clock = &radeon_legacy_get_memory_clock,
> + .set_memory_clock = NULL,
> + .set_pcie_lanes = &rv370_set_pcie_lanes,
> + .set_clock_gating = &radeon_legacy_set_clock_gating,
> + .set_surface_reg = r100_set_surface_reg,
> + .clear_surface_reg = r100_clear_surface_reg,
> + .bandwidth_update = &r100_bandwidth_update,
> + .hpd_init = &r100_hpd_init,
> + .hpd_fini = &r100_hpd_fini,
> + .hpd_sense = &r100_hpd_sense,
> + .hpd_set_polarity = &r100_hpd_set_polarity,
> + .ioctl_wait_idle = NULL,
> +};
> +
> /*
> * r420,r423,rv410
> */
> diff --git a/drivers/gpu/drm/radeon/radeon_device.c
> b/drivers/gpu/drm/radeon/radeon_device.c
> index b5c9d38..767aed8 100644
> --- a/drivers/gpu/drm/radeon/radeon_device.c
> +++ b/drivers/gpu/drm/radeon/radeon_device.c
> @@ -341,11 +341,10 @@ int radeon_asic_init(struct radeon_device *rdev)
> case CHIP_R350:
> case CHIP_RV350:
> case CHIP_RV380:
> - rdev->asic = &r300_asic;
> - if (rdev->flags & RADEON_IS_PCIE) {
> - rdev->asic->gart_tlb_flush =
> &rv370_pcie_gart_tlb_flush;
> - rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
> - }
> + if (rdev->flags & RADEON_IS_PCIE)
> + rdev->asic = &r300_asic_pcie;
> + else
> + rdev->asic = &r300_asic;
> break;
> case CHIP_R420:
> case CHIP_R423:
> --
> 1.6.3.3
>
>
> ------------------------------------------------------------------------------
> SOLARIS 10 is the OS for Data Centers - provides features such as DTrace,
> Predictive Self Healing and Award Winning ZFS. Get Solaris 10 NOW
> http://p.sf.net/sfu/solaris-dev2dev
> --
> _______________________________________________
> Dri-devel mailing list
> Dri-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/dri-devel
>
------------------------------------------------------------------------------
Download Intel® Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
--
_______________________________________________
Dri-devel mailing list
Dri-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/dri-devel
