2010/2/18 Rafał Miłecki <zaj...@gmail.com>: > W dniu 18 lutego 2010 20:39 użytkownik Rafał Miłecki <zaj...@gmail.com> > napisał: >> W dniu 18 lutego 2010 20:29 użytkownik Alex Deucher >> <alexdeuc...@gmail.com> napisał: >>> 2010/2/17 Rafał Miłecki <zaj...@gmail.com>: >>>> We kept requested and current modes in many places, depending on current >>>> state. >>>> That was useless, one place for holding that is enough. >>>> >>>> Signed-off-by: Rafał Miłecki <zaj...@gmail.com> >>>> --- >>>> Tested on my RV620, no problems. Alex: can you review this patch? It's your >>>> code I modify/remove in it. >>> >>> NACK. Why are you replacing pointers with copies of of the power >>> state structs? The idea is to keep one array of power states and >>> pointers to the current one, default one, and requested one. Then >>> comparing power states is just comparing pointers and when you change >>> the power state, you just update the pointer rather then memcpying the >>> entire struct. >> >> Then first of all we would need to reduce modes pointers. Keeping mode >> pointer in every state struct is/was useless. >> >> About introduced solution (keeping struct and memcpy to it) I >> introduced that to make hacking requested mode possible. Info from >> AtomBIOS about PCIE lanes seem to be useless (I've never seen anything >> else than 16) so I want to hack found mode for DPMS OFF to use 1 PCIE >> lane. Without keeping whole struct it would be impossible without >> overwriting original entry in array and loosing original info. > > We may also consider hacking eng/mem clocks in requested mode for DPMS > OFF. Maybe we could use chip's minimum instead lowest entry from > AtomBIOS table?
You could try, but for stability sake, we should try and stick to the tables; that's why there are there. Certain clock combinations just don't work well. Alex ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
