2010/2/18 Rafał Miłecki <zaj...@gmail.com>: > W dniu 18 lutego 2010 22:04 użytkownik Alex Deucher > <alexdeuc...@gmail.com> napisał: >> 2010/2/18 Rafał Miłecki <zaj...@gmail.com>: >>> Signed-off-by: Rafał Miłecki <zaj...@gmail.com> >>> --- >>> V2: use already implemented functions for reading/writing PCIE PORT >>> V3: fix rreg/wreg typo in macro >>> >>> Thanks Alex for reviewing! >>> --- >>> drivers/gpu/drm/radeon/r300.c | 5 ++++- >>> drivers/gpu/drm/radeon/radeon.h | 2 ++ >>> drivers/gpu/drm/radeon/radeon_asic.h | 4 ++-- >>> drivers/gpu/drm/radeon/radeon_pm.c | 2 ++ >>> 4 files changed, 10 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c >>> index 7e9f956..29ef9d8 100644 >>> --- a/drivers/gpu/drm/radeon/r300.c >>> +++ b/drivers/gpu/drm/radeon/r300.c >>> @@ -549,7 +549,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev) >>> >>> /* FIXME wait for idle */ >>> >>> - link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); >>> + if (rdev->family < CHIP_R600) >>> + link_width_cntl = >>> RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); >>> + else >>> + link_width_cntl = >>> RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); >> >> Since you also have a patch to implement setting the number of lanes, >> it would be better to create a new r600 version of get_pcie_lanes() >> since we may need other r6xx+ specific stuff in it. > > If we get to point where r6xx+ code will differ more, I'm ready to > implement that. But if that's matter of just one condition, is that > worth splitting it into two functions?
I guess it's ok for now. I just don't want to get make it too confusing later on. BTW, does it actually work? I found that generally it always reads back 0 regardless of how many lanes are enabled. Alex ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
