We already know same offsets are used for different encoders/transmitters, so
just numeric them instead naming incorrectly. Additionaly we found additional
registers needed for RV770+
Signed-off-by: Rafał Miłecki <zaj...@gmail.com>
---
drivers/gpu/drm/radeon/r600_hdmi.c | 10 +++++-----
drivers/gpu/drm/radeon/r600_reg.h | 10 +++++++---
drivers/gpu/drm/radeon/radeon_mode.h | 1 +
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c
b/drivers/gpu/drm/radeon/r600_hdmi.c
index fcc949d..4d09973 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -470,27 +470,27 @@ void r600_hdmi_init(struct drm_encoder *encoder)
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
+ radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
break;
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
switch (r600_audio_tmds_index(encoder)) {
case 0:
- radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
+ radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
break;
case 1:
- radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
+ radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2;
break;
default:
radeon_encoder->hdmi_offset = 0;
break;
}
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
+ radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
- radeon_encoder->hdmi_offset = R600_HDMI_DIG;
+ radeon_encoder->hdmi_offset = R600_HDMI_BLOCK3;
break;
default:
diff --git a/drivers/gpu/drm/radeon/r600_reg.h
b/drivers/gpu/drm/radeon/r600_reg.h
index d0e28ff..7b1d223 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -152,9 +152,9 @@
#define R600_AUDIO_STATUS_BITS 0x73d8
/* HDMI base register addresses */
-#define R600_HDMI_TMDS1 0x7400
-#define R600_HDMI_TMDS2 0x7700
-#define R600_HDMI_DIG 0x7800
+#define R600_HDMI_BLOCK1 0x7400
+#define R600_HDMI_BLOCK2 0x7700
+#define R600_HDMI_BLOCK3 0x7800
/* HDMI registers */
#define R600_HDMI_ENABLE 0x00
@@ -185,4 +185,8 @@
#define R600_HDMI_AUDIO_DEBUG_2 0xe8
#define R600_HDMI_AUDIO_DEBUG_3 0xec
+/* HDMI additional config base register addresses */
+#define R600_HDMI_CONFIG1 0x7600
+#define R600_HDMI_CONFIG2 0x7a00
+
#endif
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
b/drivers/gpu/drm/radeon/radeon_mode.h
index 1702b82..ef186a3 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -342,6 +342,7 @@ struct radeon_encoder {
struct drm_display_mode native_mode;
void *enc_priv;
int hdmi_offset;
+ int hdmi_config_offset;
int hdmi_audio_workaround;
int hdmi_buffer_status;
};
--
1.6.4.2
------------------------------------------------------------------------------
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