On Thu, Mar 18, 2010 at 9:29 PM, Suresh Siddha
<suresh.b.sid...@intel.com> wrote:
> On Thu, 2010-03-18 at 02:41 -0700, Pauli Nieminen wrote:
>> On Thu, Mar 18, 2010 at 1:52 AM, Dave Airlie <airl...@gmail.com> wrote:
>> > On Thu, Mar 18, 2010 at 6:50 AM, Pauli Nieminen <suok...@gmail.com> wrote:
>> >> Setting single memory pages at a time to wc takes a lot time in cache 
>> >> flush. To
>> >> reduce number of cache flush set_pages_array_wc and set_memory_array_wc 
>> >> can be
>> >> used to set multiple pages to WC with single cache flush.
>> >
>> > I don't think this is correct, I've cc'ed Suresh and Venki who looked
>> > at this before,
>> > but I think there is an array in the x86 code that stores the state
>> > and it only has a
>> > single bit in it, it needs to be expanded in order to at WC support.
>> >
>
> hmm, I thought we had the array variants for the WC already. I don't
> think there is any explicit reason for not having it. Correcting Venki's
> address, to see if he has anything to add.
>
>> >> +       ret = cpa_set_pages_array(pages, addrinarray,
>> >> +                       __pgprot(_PAGE_CACHE_UC_MINUS));
>> >> +       if (!ret && new_type == _PAGE_CACHE_WC)
>> >> +               ret = change_page_attr_set_clr(NULL, addrinarray,
>> >> +                                              __pgprot(_PAGE_CACHE_WC),
>> >> +                                              __pgprot(_PAGE_CACHE_MASK),
>> >> +                                              0, CPA_PAGES_ARRAY, pages);
>
> Pauli, Is there any reason for not using cpa_set_pages_array() here
> aswell?
>

cpa_set_pages_array is setting mask parameter to zero while
_set_memory_wc is passing the mask parameter. I didn't look deep
enough to the code to know why _set_memory_wc works that way.

> thanks,
> suresh
>
>

------------------------------------------------------------------------------
Download Intel&#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
--
_______________________________________________
Dri-devel mailing list
Dri-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/dri-devel

Reply via email to