Updated patch to allow you to change the display priority at runtime. Alex
On Tue, Mar 30, 2010 at 12:29 PM, Alex Deucher <alexdeuc...@gmail.com> wrote: > From 0d2509130004624ffdc21f0d1666d5ac869d124a Mon Sep 17 00:00:00 2001 > From: Alex Deucher <alexdeuc...@gmail.com> > Date: Tue, 30 Mar 2010 12:22:17 -0400 > Subject: [PATCH] drm/radeon/kms: display watermark updates > > - Add module option to force the display priority > 0 = auto, 1 = normal, 2 = high > - Default to high on r3xx/r4xx/rv515 chips > Fixes flickering problems during heavy acceleration > due to underflow to the display controllers > - Fill in minimal support for RS600 > > Signed-off-by: Alex Deucher <alexdeuc...@gmail.com> > --- > drivers/gpu/drm/radeon/radeon.h | 1 + > drivers/gpu/drm/radeon/radeon_display.c | 13 +++++++ > drivers/gpu/drm/radeon/radeon_drv.c | 4 ++ > drivers/gpu/drm/radeon/rs600.c | 23 +++++++++++++- > drivers/gpu/drm/radeon/rs600d.h | 53 > +++++++++++++++++++++++++++++++ > drivers/gpu/drm/radeon/rs690.c | 33 +++++++++++++------ > drivers/gpu/drm/radeon/rs690d.h | 3 ++ > drivers/gpu/drm/radeon/rv515.c | 33 +++++++++++++------ > 8 files changed, 142 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h > index 55da095..d300486 100644 > --- a/drivers/gpu/drm/radeon/radeon.h > +++ b/drivers/gpu/drm/radeon/radeon.h > @@ -91,6 +91,7 @@ extern int radeon_tv; > extern int radeon_new_pll; > extern int radeon_dynpm; > extern int radeon_audio; > +extern int radeon_disp_priority; > > /* > * Copy from radeon_drv.h so we don't have to include both and have > conflicting > diff --git a/drivers/gpu/drm/radeon/radeon_display.c > b/drivers/gpu/drm/radeon/radeon_display.c > index eca714c..600f7b1 100644 > --- a/drivers/gpu/drm/radeon/radeon_display.c > +++ b/drivers/gpu/drm/radeon/radeon_display.c > @@ -996,6 +996,19 @@ int radeon_modeset_init(struct radeon_device *rdev) > return ret; > } > > + /* adjustment options for the display watermarks */ > + if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { > + /* set display priority to high for r3xx, rv515 chips > + * this avoids flickering due to underflow to the > + * display controllers during heavy acceleration. > + */ > + if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) > + rdev->disp_priority = 2; > + else > + rdev->disp_priority = 0; > + } else > + rdev->disp_priority = radeon_disp_priority; > + > /* check combios for a valid hardcoded EDID - Sun servers */ > if (!rdev->is_atom_bios) { > /* check for hardcoded EDID in BIOS */ > diff --git a/drivers/gpu/drm/radeon/radeon_drv.c > b/drivers/gpu/drm/radeon/radeon_drv.c > index 54ec049..6fd511e 100644 > --- a/drivers/gpu/drm/radeon/radeon_drv.c > +++ b/drivers/gpu/drm/radeon/radeon_drv.c > @@ -92,6 +92,7 @@ int radeon_tv = 1; > int radeon_new_pll = -1; > int radeon_dynpm = -1; > int radeon_audio = 1; > +int radeon_disp_priority = 0; > > MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); > module_param_named(no_wb, radeon_no_wb, int, 0444); > @@ -135,6 +136,9 @@ module_param_named(dynpm, radeon_dynpm, int, 0444); > MODULE_PARM_DESC(audio, "Audio enable (0 = disable)"); > module_param_named(audio, radeon_audio, int, 0444); > > +MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = > normal, 2 = high)"); > +module_param_named(disp_priority, radeon_disp_priority, int, 0444); > + > static int radeon_suspend(struct drm_device *dev, pm_message_t state) > { > drm_radeon_private_t *dev_priv = dev->dev_private; > diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c > index 7d8ae42..edd5cd8 100644 > --- a/drivers/gpu/drm/radeon/rs600.c > +++ b/drivers/gpu/drm/radeon/rs600.c > @@ -554,7 +554,28 @@ void rs600_mc_init(struct radeon_device *rdev) > > void rs600_bandwidth_update(struct radeon_device *rdev) > { > - /* FIXME: implement, should this be like rs690 ? */ > + struct drm_display_mode *mode0 = NULL; > + struct drm_display_mode *mode1 = NULL; > + u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; > + /* FIXME: implement full support */ > + > + if (rdev->mode_info.crtcs[0]->base.enabled) > + mode0 = &rdev->mode_info.crtcs[0]->base.mode; > + if (rdev->mode_info.crtcs[1]->base.enabled) > + mode1 = &rdev->mode_info.crtcs[1]->base.mode; > + > + rs690_line_buffer_adjust(rdev, mode0, mode1); > + > + if (rdev->disp_priority == 2) { > + d1mode_priority_a_cnt = > RREG32(R_006548_D1MODE_PRIORITY_A_CNT); > + d2mode_priority_a_cnt = > RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); > + d1mode_priority_a_cnt |= > S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); > + d2mode_priority_a_cnt |= > S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); > + WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); > + WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); > + WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); > + WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); > + } > } > > uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) > diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h > index 00896c5..08c4beb 100644 > --- a/drivers/gpu/drm/radeon/rs600d.h > +++ b/drivers/gpu/drm/radeon/rs600d.h > @@ -581,4 +581,57 @@ > #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) > #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF > > +#define R_006548_D1MODE_PRIORITY_A_CNT 0x006548 > +#define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) > +#define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) > +#define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000 > +#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) > +#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) > +#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF > +#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) > +#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) > +#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF > +#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) > +#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) > +#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF > +#define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C > +#define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) > +#define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) > +#define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000 > +#define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) > +#define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) > +#define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF > +#define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) > +#define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) > +#define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF > +#define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) > +#define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) > +#define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF > +#define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48 > +#define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) > +#define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) > +#define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000 > +#define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) > +#define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) > +#define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF > +#define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) > +#define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) > +#define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF > +#define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) > +#define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) > +#define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF > +#define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C > +#define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) > +#define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) > +#define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000 > +#define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) > +#define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) > +#define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF > +#define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) > +#define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) > +#define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF > +#define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) > +#define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) > +#define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF > + > #endif > diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c > index 4a1822a..112e811 100644 > --- a/drivers/gpu/drm/radeon/rs690.c > +++ b/drivers/gpu/drm/radeon/rs690.c > @@ -398,7 +398,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev) > struct drm_display_mode *mode1 = NULL; > struct rs690_watermark wm0; > struct rs690_watermark wm1; > - u32 tmp; > + u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; > fixed20_12 priority_mark02, priority_mark12, fill_rate; > fixed20_12 a, b; > > @@ -411,7 +411,8 @@ void rs690_bandwidth_update(struct radeon_device *rdev) > * modes if the user specifies HIGH for displaypriority > * option. > */ > - if (rdev->disp_priority == 2) { > + if ((rdev->disp_priority == 2) && > + ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { > tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); > tmp &= C_000104_MC_DISP0R_INIT_LAT; > tmp &= C_000104_MC_DISP1R_INIT_LAT; > @@ -486,10 +487,16 @@ void rs690_bandwidth_update(struct radeon_device *rdev) > priority_mark12.full = 0; > if (wm1.priority_mark_max.full > priority_mark12.full) > priority_mark12.full = wm1.priority_mark_max.full; > - WREG32(R_006548_D1MODE_PRIORITY_A_CNT, > rfixed_trunc(priority_mark02)); > - WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, > rfixed_trunc(priority_mark02)); > - WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, > rfixed_trunc(priority_mark12)); > - WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, > rfixed_trunc(priority_mark12)); > + d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); > + d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); > + if (rdev->disp_priority == 2) { > + d1mode_priority_a_cnt |= > S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); > + d2mode_priority_a_cnt |= > S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); > + } > + WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); > + WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); > + WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); > + WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); > } else if (mode0) { > if (rfixed_trunc(wm0.dbpp) > 64) > a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); > @@ -516,8 +523,11 @@ void rs690_bandwidth_update(struct radeon_device *rdev) > priority_mark02.full = 0; > if (wm0.priority_mark_max.full > priority_mark02.full) > priority_mark02.full = wm0.priority_mark_max.full; > - WREG32(R_006548_D1MODE_PRIORITY_A_CNT, > rfixed_trunc(priority_mark02)); > - WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, > rfixed_trunc(priority_mark02)); > + d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); > + if (rdev->disp_priority == 2) > + d1mode_priority_a_cnt |= > S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); > + WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); > + WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); > WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, > S_006D48_D2MODE_PRIORITY_A_OFF(1)); > WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, > @@ -548,12 +558,15 @@ void rs690_bandwidth_update(struct radeon_device *rdev) > priority_mark12.full = 0; > if (wm1.priority_mark_max.full > priority_mark12.full) > priority_mark12.full = wm1.priority_mark_max.full; > + d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); > + if (rdev->disp_priority == 2) > + d2mode_priority_a_cnt |= > S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); > WREG32(R_006548_D1MODE_PRIORITY_A_CNT, > S_006548_D1MODE_PRIORITY_A_OFF(1)); > WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, > S_00654C_D1MODE_PRIORITY_B_OFF(1)); > - WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, > rfixed_trunc(priority_mark12)); > - WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, > rfixed_trunc(priority_mark12)); > + WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); > + WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); > } > } > > diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h > index 62d31e7..36e6398 100644 > --- a/drivers/gpu/drm/radeon/rs690d.h > +++ b/drivers/gpu/drm/radeon/rs690d.h > @@ -182,6 +182,9 @@ > #define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) > #define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) > #define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF > +#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) > +#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) > +#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF > #define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) > #define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) > #define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF > diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c > index 3350023..d985db9 100644 > --- a/drivers/gpu/drm/radeon/rv515.c > +++ b/drivers/gpu/drm/radeon/rv515.c > @@ -926,7 +926,7 @@ void rv515_bandwidth_avivo_update(struct > radeon_device *rdev) > struct drm_display_mode *mode1 = NULL; > struct rv515_watermark wm0; > struct rv515_watermark wm1; > - u32 tmp; > + u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; > fixed20_12 priority_mark02, priority_mark12, fill_rate; > fixed20_12 a, b; > > @@ -994,10 +994,16 @@ void rv515_bandwidth_avivo_update(struct > radeon_device *rdev) > priority_mark12.full = 0; > if (wm1.priority_mark_max.full > priority_mark12.full) > priority_mark12.full = wm1.priority_mark_max.full; > - WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); > - WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); > - WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); > - WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); > + d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); > + d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); > + if (rdev->disp_priority == 2) { > + d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; > + d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; > + } > + WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); > + WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); > + WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); > + WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); > } else if (mode0) { > if (rfixed_trunc(wm0.dbpp) > 64) > a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); > @@ -1024,8 +1030,11 @@ void rv515_bandwidth_avivo_update(struct > radeon_device *rdev) > priority_mark02.full = 0; > if (wm0.priority_mark_max.full > priority_mark02.full) > priority_mark02.full = wm0.priority_mark_max.full; > - WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); > - WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); > + d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); > + if (rdev->disp_priority == 2) > + d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; > + WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); > + WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); > WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); > WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); > } else { > @@ -1054,10 +1063,13 @@ void rv515_bandwidth_avivo_update(struct > radeon_device *rdev) > priority_mark12.full = 0; > if (wm1.priority_mark_max.full > priority_mark12.full) > priority_mark12.full = wm1.priority_mark_max.full; > + d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); > + if (rdev->disp_priority == 2) > + d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; > WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); > WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); > - WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); > - WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); > + WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); > + WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); > } > } > > @@ -1076,7 +1088,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev) > * modes if the user specifies HIGH for displaypriority > * option. > */ > - if (rdev->disp_priority == 2) { > + if ((rdev->disp_priority == 2) && > + (rdev->family == CHIP_RV515)) { > tmp = RREG32_MC(MC_MISC_LAT_TIMER); > tmp &= ~MC_DISP1R_INIT_LAT_MASK; > tmp &= ~MC_DISP0R_INIT_LAT_MASK; > -- > 1.5.6.3 >
0001-drm-radeon-kms-display-watermark-updates-v2.patch
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