From: Dave Airlie <airl...@redhat.com>
On constrained r100 systems compiz would fail to start due to a lack
of memory, we can just fallback place the objects rather than completely
failing it works a lot better.
v2:
fixes issue identified by Michel when pinning could happen in a busy placement
domain.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
drivers/gpu/drm/radeon/radeon.h | 4 +++-
drivers/gpu/drm/radeon/radeon_object.c | 22 +++++++++++++---------
drivers/gpu/drm/radeon/radeon_ttm.c | 6 +++---
3 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e912098..a23a6ab 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -240,7 +240,9 @@ struct radeon_bo {
struct list_head list;
/* Protected by tbo.reserved */
u32 placements[3];
+ u32 busy_placements[3];
struct ttm_placement placement;
+ struct ttm_placement busy_placement;
struct ttm_buffer_object tbo;
struct ttm_bo_kmap_obj kmap;
unsigned pin_count;
@@ -1227,7 +1229,7 @@ extern void radeon_surface_init(struct radeon_device
*rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int
enable);
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int
enable);
-extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32
domain);
+extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32
domain, bool pinned);
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc
*mc, u64 base);
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c
b/drivers/gpu/drm/radeon/radeon_object.c
index 6a8617b..ab3bc7b 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -64,17 +64,21 @@ bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo)
return false;
}
-void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
+void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain, bool
pinned)
{
- u32 c = 0;
+ u32 c = 0, b = 0;
rbo->placement.fpfn = 0;
rbo->placement.lpfn = 0;
rbo->placement.placement = rbo->placements;
- rbo->placement.busy_placement = rbo->placements;
+ rbo->placement.busy_placement = rbo->busy_placements;
if (domain & RADEON_GEM_DOMAIN_VRAM)
rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
TTM_PL_FLAG_VRAM;
+ /* add busy placement to TTM if VRAM is only option */
+ if (domain == RADEON_GEM_DOMAIN_VRAM && pinned == false) {
+ rbo->busy_placements[b++] = TTM_PL_MASK_CACHING |
TTM_PL_FLAG_TT;
+ }
if (domain & RADEON_GEM_DOMAIN_GTT)
rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
if (domain & RADEON_GEM_DOMAIN_CPU)
@@ -82,7 +86,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo,
u32 domain)
if (!c)
rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
rbo->placement.num_placement = c;
- rbo->placement.num_busy_placement = c;
+ rbo->placement.num_busy_placement = b;
}
int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
@@ -110,7 +114,7 @@ int radeon_bo_create(struct radeon_device *rdev, struct
drm_gem_object *gobj,
bo->surface_reg = -1;
INIT_LIST_HEAD(&bo->list);
- radeon_ttm_placement_from_domain(bo, domain);
+ radeon_ttm_placement_from_domain(bo, domain, false);
/* Kernel allocation are uninterruptible */
r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
&bo->placement, 0, 0, !kernel, NULL, size,
@@ -185,7 +189,7 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64
*gpu_addr)
*gpu_addr = radeon_bo_gpu_offset(bo);
return 0;
}
- radeon_ttm_placement_from_domain(bo, domain);
+ radeon_ttm_placement_from_domain(bo, domain, true);
if (domain == RADEON_GEM_DOMAIN_VRAM) {
/* force to pin into visible video ram */
bo->placement.lpfn = bo->rdev->mc.visible_vram_size >>
PAGE_SHIFT;
@@ -325,10 +329,10 @@ int radeon_bo_list_validate(struct list_head *head)
if (!bo->pin_count) {
if (lobj->wdomain) {
radeon_ttm_placement_from_domain(bo,
- lobj->wdomain);
+ lobj->wdomain,
false);
} else {
radeon_ttm_placement_from_domain(bo,
- lobj->rdomain);
+ lobj->rdomain,
false);
}
r = ttm_bo_validate(&bo->tbo, &bo->placement,
true, false, false);
@@ -516,7 +520,7 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object
*bo)
offset = bo->mem.mm_node->start << PAGE_SHIFT;
if ((offset + size) > rdev->mc.visible_vram_size) {
/* hurrah the memory is not visible ! */
- radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_VRAM);
+ radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_VRAM, false);
rbo->placement.lpfn = rdev->mc.visible_vram_size >>
PAGE_SHIFT;
r = ttm_bo_validate(bo, &rbo->placement, false, true,
false);
if (unlikely(r != 0))
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index af98f45..6557b44 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -205,13 +205,13 @@ static void radeon_evict_flags(struct ttm_buffer_object
*bo,
switch (bo->mem.mem_type) {
case TTM_PL_VRAM:
if (rbo->rdev->cp.ready == false)
- radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_CPU);
+ radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_CPU, false);
else
- radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_GTT);
+ radeon_ttm_placement_from_domain(rbo,
RADEON_GEM_DOMAIN_GTT, false);
break;
case TTM_PL_TT:
default:
- radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
+ radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU,
false);
}
*placement = rbo->placement;
}
--
1.6.6.1
------------------------------------------------------------------------------
--
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