On Fri, 26 Mar 2010 11:07:19 -0700 Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> On 945, vblank delivery alone seems unreliable. The PIPE*STAT bits get > set correctly, but interrupts occur at a low frequency relative to > refresh. If we enable VSYNC interrupts as well however (even though we > only check for VBLANK interrupts when handling) we get the right > frequency. Increases OA performance on my AspireOne by about 300% with > the new DRI2 bits, which rely on high frequency vblank events. > > Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org> > --- Ignore this patch; it's still broken. Working on a fix now. -- Jesse Barnes, Intel Open Source Technology Center ------------------------------------------------------------------------------ -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
