Andrew Gallatin wrote:
> Garrett D'Amore wrote:
>> Masa Murayama wrote:
>>> ----- Original Message -----
>>>
>>>>
>>> Typical sparc IOMMU DVMA range is 0xff000000 - 0xffffffff, the highest
>>> 16Mbyte in PCI memory sparce. Threfore, PCI master devices *must*
>>> support the range for dma.
>>>
>>> Recently I saw the same message for BCM4401 driver on sparc,
>>> the divece only supports the dma range of 0x00000000 - 0x40000000,
>>> the lowest 1Gbyte. So bcm4401 doesn't work on sparc.
>>
>> Right. An interesting data point about SPARC -- I had forgotten that
>> limitation. There are a few other devices I've run into in the past
>> that had this limitation.
>
> Could somebody elaborate on DVMA?
>
> I thought DVMA was some kind of optimization that was supposed
> to be avoided in new drivers.. Am I mis-remembering?
It is indeed an optimization. Basically, it allows one to pre-reserve
some page table entries in the sparc IOMMU, so that you can reuse the
entries on an as needed basis. In the ancient pre 2.6 days, DMA was
really slow, and DVMA was a hack to work around slowness in the DDI.
These days, DVMA is still faster, but it has limitations -- its not
always available on a given SPARC machine, and it simply isn't available
at all on x86 systems. The drivers that use it (hme is a good example)
often have incredibly poor handling of the failure cases when dvma is
unavailable, yielding ridiculously poor DMA performance.
Its also not DDI compliant.
Intelligent use of DDI compliant DMA (reusing handles, and sometimes
even reusing actual bindings via either bcopy or loanup) largely
obviates any need for DVMA.
-- Garrett
>
> Thanks,
>
> Drew
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