Steven Stallion wrote:
>> Perhaps you need to enable 16-bit transfers on the device?
>>
>
> Now that I think about it, probably not. I am trying to read from the PROM
> prior to initializing the device (I believe Masa does something simliar,
> except he is explicitly setting WTS - which is probably what I am missing
> here).
>
> Beyond setting WTS on the device, are there any other bits I need to set
> WRT PCI? PCI_COMM_IO and PCI_COMM_MAE are set as mentioned in the
> specification.
>
Usually you don't need both PCI_COMM_IO *and* PCI_COMM_MAE... either one
or the other is sufficient. (Which one will depend on the device and
what BAR(s) you are using.)
>
>> Are you making sure that you're using aligned addresses? (You can not
>> do a 16-bit transfer from an odd-byte address on a SPARC system.)
>>
>
> It's on an even offset, but let me double check; I havent checked what
> base address was given for the regs map.
>
PCI base addresses are by definition evenly aligned. (Actually, they
are required to be aligned on 16 byte addresses -- i.e. 128 bit aligned.)
-- Garrett
>
>> -- Garrett
>>
>> Steven Stallion wrote:
>>
>>> Masa-san/Garrett,
>>>
>>> I've reverted everything to PIO on the RTL8029. Everything works
>>> perfectly for 8-bit transfers, however this is far from optimal (RDMA
>>> reads essentially require a dummy read for each byte).
>>>
>>> I am finding that if I enable WTS (16-bit) transfers, an attempt to read
>>> the first 6 bytes of PROM results in a panic:
>>>
>>> NOTICE: SUNW-MSG-ID: SUNOS-8000-0G, TYPE: Error, VER: 1, SEVERITY: Major
>>>
>>>
>>> panic[cpu1]/thread=2a100aa7ca0:
>>> BERR Error(s)
>>>
>>> The offending line is a ddi_get16() call with the same base address as
>>> the (working) byte transfer.
>>>
>>> Any ideas?
>>>
>>> Steve
>>> _______________________________________________
>>> driver-discuss mailing list
>>> driver-discuss@opensolaris.org
>>> http://mail.opensolaris.org/mailman/listinfo/driver-discuss
>>>
>>>
>>
>
>
>
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