Document new DVFS OPP table and voltage regulator properties of the
PWM controller.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 74c41e34c3b6..d4d1c44a2c04 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -32,6 +32,17 @@ The PWM node will have following optional properties.
pinctrl-names: Pin state names. Must be "default" and "sleep".
pinctrl-0: phandle for the default/active state of pin configurations.
pinctrl-1: phandle for the sleep state of pin configurations.
+core-supply: phandle for voltage regulator of the SoC "core" power domain.
+
+operating-points-v2: see ../bindings/opp/opp.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: One bitfield indicating:
+ On Tegra20: SoC process ID mask
+ On Tegra30+: SoC speedo ID mask
+
+ A bitwise AND is performed against the value and if any bit
+ matches, the OPP gets enabled.
Example:
@@ -42,6 +53,8 @@ Example:
clocks = <&tegra_car 17>;
resets = <&tegra_car 17>;
reset-names = "pwm";
+ operating-points-v2 = <&dvfs_opp_table>;
+ core-supply = <&vdd_core>;
};
--
2.27.0
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