From: Alan Tull <at...@opensource.altera.com>

Add documentation under drivers/staging for new fpga manager's
sysfs interface.

Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v5  : (actually second version, but keeping version numbers
      aligned with rest of patch series)
      Move document to drivers/staging/fpga/Documentation/ABI

v6  : No change in this patch for v6 of the patch set
v7  : No change in this patch for v7 of the patch set
v8  : No change in this patch for v8 of the patch set

v9  : Remove 'firmware' and 'reset' files
      Update state strings

v10 : Clarifications about state attribute
      Move to Documentation/ABI/testing/

v11 : No change in this patch for v11 of the patch set
---
 Documentation/ABI/testing/sysfs-class-fpga-manager |   37 ++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-manager

diff --git a/Documentation/ABI/testing/sysfs-class-fpga-manager 
b/Documentation/ABI/testing/sysfs-class-fpga-manager
new file mode 100644
index 0000000..23056c5
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-fpga-manager
@@ -0,0 +1,37 @@
+What:          /sys/class/fpga_manager/<fpga>/name
+Date:          August 2015
+KernelVersion: 4.3
+Contact:       Alan Tull <at...@opensource.altera.com>
+Description:   Name of low level fpga manager driver.
+
+What:          /sys/class/fpga_manager/<fpga>/state
+Date:          August 2015
+KernelVersion: 4.3
+Contact:       Alan Tull <at...@opensource.altera.com>
+Description:   Read fpga manager state as a string.
+               The intent is to provide enough detail that if something goes
+               wrong during FPGA programming (something that the driver can't
+               fix) then userspace can know, i.e. if the firmware request
+               fails, that could be due to not being able to find the firmware
+               file.
+
+               This is a superset of FPGA states and fpga manager driver
+               states.  The fpga manager driver is walking through these steps
+               to get the FPGA into a known operating state.  It's a sequence,
+               though some steps may get skipped.  Valid FPGA states will vary
+               by manufacturer; this is a superset.
+
+               * unknown               = can't determine state
+               * power off             = FPGA power is off
+               * power up              = FPGA reports power is up
+               * reset                 = FPGA held in reset state
+               * firmware request      = firmware class request in progress
+               * firmware request error = firmware request failed
+               * write init            = preparing FPGA for programming
+               * write init error      = Error while preparing FPGA for
+                                         programming
+               * write                 = FPGA ready to receive image data
+               * write error           = Error while programming
+               * write complete        = Doing post programming steps
+               * write complete error  = Error while doing post programming
+               * operating             = FPGA is programmed and operating
-- 
1.7.9.5

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