Add support for accessing the device through DMA because CPU is
unnecessarily used when DMA can do the job. Coherent mapping is allocated
by means of dma_alloc_coherent so that the device and CPU are in sync.
Signed-off-by: Shraddha Barke <shraddha.6...@gmail.com>
---
drivers/staging/goldfish/goldfish_nand.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/goldfish/goldfish_nand.c
b/drivers/staging/goldfish/goldfish_nand.c
index 623353db5..2d3fb8d 100644
--- a/drivers/staging/goldfish/goldfish_nand.c
+++ b/drivers/staging/goldfish/goldfish_nand.c
@@ -27,6 +27,7 @@
#include <linux/mutex.h>
#include <linux/goldfish.h>
#include <asm/div64.h>
+#include <linux/dma-mapping.h>
#include "goldfish_nand_reg.h"
@@ -284,7 +285,8 @@ invalid_arg:
static int nand_setup_cmd_params(struct platform_device *pdev,
struct goldfish_nand *nand)
{
- u64 paddr;
+ void *addr;
+ dma_addr_t dma_handle;
unsigned char __iomem *base = nand->base;
nand->cmd_params = devm_kzalloc(&pdev->dev,
@@ -292,9 +294,14 @@ static int nand_setup_cmd_params(struct platform_device
*pdev,
if (!nand->cmd_params)
return -1;
- paddr = __pa(nand->cmd_params);
- writel((u32)(paddr >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
- writel((u32)paddr, base + NAND_CMD_PARAMS_ADDR_LOW);
+ addr = dma_alloc_coherent(&pdev->dev, sizeof(struct cmd_params),
+ &dma_handle, GFP_KERNEL | GFP_DMA);
+ if (!addr) {
+ dev_err(&pdev->dev, "allocate buffer failed\n");
+ return -ENOMEM;
+ }
+ writel((u32)(dma_handle >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
+ writel((u32)dma_handle, base + NAND_CMD_PARAMS_ADDR_LOW);
return 0;
}
--
2.1.4
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