Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
arch/arm/boot/dts/tegra20.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 7c85f97f72ea..fb485a5e63d7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -249,6 +249,22 @@
*/
};
+ vde@6001a000 {
+ compatible = "nvidia,tegra20-vde";
+ reg = <0x6001a000 0x3D00 /* VDE registers */
+ 0x40000400 0x3FC00>; /* IRAM area */
+ reg-names = "regs", "iram";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, /* UCQ error
interrupt */
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token
interrupt */
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V
interrupt */
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, /* BSE-A
interrupt */
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt
*/
+ interrupt-names = "ucq-error", "sync-token", "bsev", "bsea",
"sxe";
+ clocks = <&tegra_car TEGRA20_CLK_VDE>;
+ resets = <&tegra_car 61>;
+ reset-names = "vde";
+ };
+
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64 /* Chip revision */
--
2.14.1
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