This commit simplifies and clean a lot of stuff related with pci
reads and writes. It deletes a lot of not needed at all functions
and use kernel arch operations read[b,w,l] and write[b,w,l] instead
of use custom macros. It also include one function helper called
'mt7621_pci_get_cfgaddr' to easily obtain config address. Also to
get pci base address a global 'mt7621_pci_base' variable has been
included and initialized as a pointer to RALINK_PCI_BASE in driver
probe function. With this changes LOC is clearly decreased and
readability is increased.
Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 178 +++++++++++---------------------
1 file changed, 58 insertions(+), 120 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c12447d..dabe5c4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -113,23 +113,6 @@
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
-#define MV_WRITE(ofs, data) \
- *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define MV_READ(ofs, data) \
- *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_READ_DATA(ofs) \
- le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_16(ofs, data) \
- *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data) \
- *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data) \
- *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data) \
- *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
-
#define RALINK_PCI_MM_MAP_BASE 0x60000000
#define RALINK_PCI_IO_MAP_BASE 0x1e160000
@@ -173,123 +156,75 @@
#define MEMORY_BASE 0x0
static int pcie_link_status = 0;
-#define PCI_ACCESS_READ_1 0
-#define PCI_ACCESS_READ_2 1
-#define PCI_ACCESS_READ_4 2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
+static void __iomem *mt7621_pci_base;
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned int where, u32 *data)
+static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+ unsigned int func, unsigned int where)
{
- unsigned int slot = PCI_SLOT(devfn);
- u8 func = PCI_FUNC(devfn);
- uint32_t address_reg, data_reg;
- unsigned int address;
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+ 0x80000000);
+}
+
+static int
+pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ u32 address_reg, data_reg;
+ u32 address;
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) |
- (func << 8) | (where & 0xfc) | 0x80000000;
- MV_WRITE(address_reg, address);
+ address = (((where & 0xF00) >> 8) << 24) |
+ mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where);
- switch (access_type) {
- case PCI_ACCESS_WRITE_1:
- MV_WRITE_8(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_2:
- MV_WRITE_16(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_4:
- MV_WRITE(data_reg, *data);
- break;
- case PCI_ACCESS_READ_1:
- MV_READ_8(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_2:
- MV_READ_16(data_reg+(where&0x3), data);
+ writel(address, mt7621_pci_base + address_reg);
+
+ switch (size) {
+ case 1:
+ *val = readb(mt7621_pci_base + data_reg + (where & 0x3));
break;
- case PCI_ACCESS_READ_4:
- MV_READ(data_reg, data);
+ case 2:
+ *val = readw(mt7621_pci_base + data_reg + (where & 0x3));
break;
- default:
- printk("no specify access type\n");
+ case 4:
+ *val = readl(mt7621_pci_base + data_reg);
break;
}
- return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
- return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
- return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
- return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
- if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where,
(u32 *)&val))
- return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
+pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
{
- if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
- return -1;
+ u32 address_reg, data_reg;
+ u32 address;
- return PCIBIOS_SUCCESSFUL;
-}
+ address_reg = RALINK_PCI_CONFIG_ADDR;
+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
- return -1;
+ address = (((where & 0xF00) >> 8) << 24) |
+ mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where);
- return PCIBIOS_SUCCESSFUL;
-}
+ writel(address, mt7621_pci_base + address_reg);
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 *val)
-{
switch (size) {
case 1:
- return read_config_byte(bus, devfn, where, (u8 *) val);
+ writeb((u8)val, mt7621_pci_base + data_reg + (where & 0x3));
+ break;
case 2:
- return read_config_word(bus, devfn, where, (u16 *) val);
- default:
- return read_config_dword(bus, devfn, where, val);
+ writew((u16)val, mt7621_pci_base + data_reg + (where & 0x3));
+ break;
+ case 4:
+ writel(val, mt7621_pci_base + data_reg);
+ break;
}
-}
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 val)
-{
- switch (size) {
- case 1:
- return write_config_byte(bus, devfn, where, (u8) val);
- case 2:
- return write_config_word(bus, devfn, where, (u16) val);
- default:
- return write_config_dword(bus, devfn, where, val);
- }
+ return PCIBIOS_SUCCESSFUL;
}
struct pci_ops mt7621_pci_ops = {
@@ -306,29 +241,31 @@ static struct pci_controller mt7621_controller = {
};
static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
long reg, unsigned long *val)
+read_config(unsigned long bus, unsigned long dev, unsigned long func,
+ unsigned long reg, unsigned long *val)
{
- unsigned int address_reg, data_reg, address;
+ u32 address_reg, data_reg, address;
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func
<< 8) | (reg & 0xfc) | 0x80000000 ;
- MV_WRITE(address_reg, address);
- MV_READ(data_reg, val);
- return;
+ address = (((reg & 0xF00) >> 8) << 24) |
+ mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ writel(address, mt7621_pci_base + address_reg);
+ *val = readl(mt7621_pci_base + data_reg);
}
static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
unsigned long reg, unsigned long val)
+write_config(unsigned long bus, unsigned long dev, unsigned long func,
+ unsigned long reg, unsigned long val)
{
- unsigned int address_reg, data_reg, address;
+ u32 address_reg, data_reg, address;
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func
<< 8) | (reg & 0xfc) | 0x80000000 ;
- MV_WRITE(address_reg, address);
- MV_WRITE(data_reg, val);
- return;
+ address = (((reg & 0xF00) >> 8) << 24) |
+ mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ writel(address, mt7621_pci_base + address_reg);
+ writel(val, mt7621_pci_base + data_reg);
}
int
@@ -479,6 +416,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
{
unsigned long val = 0;
+ mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
iomem_resource.start = 0;
iomem_resource.end = ~0;
ioport_resource.start = 0;
--
2.7.4
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