New driver for pci phy has been added, as well as. pci driver has been
changed to use kernel's generic PHY API. Add related PCI PHY bindings
accordly.
Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 71f069d59ad8..0cbc298ed457 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -424,6 +424,8 @@
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
+ phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
@@ -449,4 +451,33 @@
bus-range = <0x00 0xff>;
};
};
+
+ pcie0_phy: pcie-phy@1a149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1a149000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie0_port: pcie-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ pcie1_port: pcie-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ pcie1_phy: pcie-phy@1a14a000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1a14a000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie2_port: pcie-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
--
2.19.1
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