[PATCH 1/4] staging: mt7621-pci: disable pcie port clock if there is no pcie link

[Sergio Paracuellos]

When there is no pcie link detected we have to properly disable the
port pcie clock.

Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index de09bda0b4cd..f6b91b29fb9c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -45,6 +45,7 @@
 #define PCIE_FTS_NUM_L0(x)             ((x) & 0xff << 8)
 
 /* rt_sysc_membase relative registers */
+#define RALINK_CLKCFG1                 0x30
 #define RALINK_PCIE_CLK_GEN            0x7c
 #define RALINK_PCIE_CLK_GEN1           0x80
 
@@ -221,6 +222,11 @@ static inline bool mt7621_pcie_port_is_linkup(struct 
mt7621_pcie_port *port)
        return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 
0;
 }
 
+static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
+{
+       rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
+}
+
 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
 {
        u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
@@ -475,6 +481,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
                                slot);
                        phy_power_off(port->phy);
                        mt7621_control_assert(port);
+                       mt7621_pcie_port_clk_disable(port);
                        port->enabled = false;
                }
        }
-- 
2.19.1

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