[PATCH] staging: mt7621-pci: enable clock bit for each port

[Sergio Paracuellos]

The clock related code concerns me from the very beginning because
there are some set ups got from legacy driver that are not documented
anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1'
register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed
at all and the proper thing to do is just enable the clock bit for each
pcie port. Hence remove useless code and do the right thing which is
setting up the clock bit for each port enabled.

Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
Changes are only compile-tested.

 drivers/staging/mt7621-pci/pci-mt7621.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1f860c5ef588..770dabd3a70d 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -45,8 +45,6 @@
 
 /* rt_sysc_membase relative registers */
 #define RALINK_CLKCFG1                 0x30
-#define RALINK_PCIE_CLK_GEN            0x7c
-#define RALINK_PCIE_CLK_GEN1           0x80
 
 /* Host-PCI bridge registers */
 #define RALINK_PCI_PCICFG_ADDR         0x0000
@@ -85,10 +83,6 @@
 #define PCIE_PORT_CLK_EN(x)            BIT(24 + (x))
 #define PCIE_PORT_LINKUP               BIT(0)
 
-#define PCIE_CLK_GEN_EN                        BIT(31)
-#define PCIE_CLK_GEN_DIS               0
-#define PCIE_CLK_GEN1_DIS              GENMASK(30, 24)
-#define PCIE_CLK_GEN1_EN               (BIT(27) | BIT(25))
 #define MEMORY_BASE                    0x0
 #define PERST_MODE_MASK                        GENMASK(11, 10)
 #define PERST_MODE_GPIO                        BIT(10)
@@ -233,6 +227,11 @@ static inline bool mt7621_pcie_port_is_linkup(struct 
mt7621_pcie_port *port)
        return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 
0;
 }
 
+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
+{
+       rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
+}
+
 static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
 {
        rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
@@ -501,11 +500,6 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie 
*pcie)
                }
        }
 
-       rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-       rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
-       rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
-       rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
-       msleep(50);
        reset_control_deassert(pcie->rst);
 }
 
@@ -542,6 +536,7 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie 
*pcie)
 
        list_for_each_entry(port, &pcie->ports, list) {
                if (port->enabled) {
+                       mt7621_pcie_port_clk_enable(port);
                        mt7621_pcie_enable_port(port);
                        dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
                        num_slots_enabled++;
-- 
2.25.1

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