On Thu, Feb 16, 2017 at 7:53 AM, Kieran Tyrrell <kie...@sienda.com> wrote: > Hi, > > We are developing a system using an i210 with an ARM SoC, and require multi > queue support, but the SoC doesn’t support MSI-X. > > Looking through the sources it appears it would take considerable effort to > modify igb to support multiple queues with legacy or MSI interrupts. > > Has anyone already attempted this?! Is there any branch or patch available > to use as a starting point?! > > Thanks and best regards, > > Kieran Tyrrell.
I'm assuming the reason why you need multiple queues is for some sort of QoS setup. Would I be guessing correctly? If not, could you explain further what the use case is? The igb driver was pretty much built around the one Tx/Rx queue pair per interrupt design. What you may do is look at the ixgbe driver and see what would be involved in copying over the code that allowed for multiple queues per interrupt. Part of the reason for supporting that is DCB which is essentially hardware QoS. It would still require some additional changes beyond that though since even ixgbe was setup to only use one queue pair when MSI-X was not supported, but it should be possible to run multiple queues without having to use MSI-X interrupts. Hope the explanation helps. - Alex ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
