Grant Edwards <[EMAIL PROTECTED]> writes: > There are no memory alignment or bus-error exceptions in the > NIOS2 processor and misaligned accesses are forbidden. The > CPU's reference manual states that misaligned accesses result > in "undefined operation". Strict interpreation of that allows > the CPU to do absolutely anything when a misaligned operation > occurs. My guess is that instruction execution continues > normally with an undefined value in the destination register, > but the spec is pretty clear that it's simply not allowed, and > CPU can do absolutely anything if it does happen.
The usual thing that happens is that the CPU ignores the least significant 1 or 2 bits of the address, so misaligned accesses are converted to aligned accesses silently. This used to be the default for ARM, but it now has an option to raise an alignment exception. > The only hardware exceptions that can be caused by software > are: > > trap > break > valid but unimplemented instruction Sadly, it looks like you are out of luck. Disabling the hardware part of these tests seems the only thing to do. -- Nick Garnett eCos Kernel Architect http://www.ecoscentric.com The eCos and RedBoot experts http://www.ecoscentric.com/legal Legal info, address and number -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
