On 2008-04-02, Andrew Lunn <[EMAIL PROTECTED]> wrote:
>> Yes. I think providing an official way how to use the FIQ with
>> lowest possible overhead under eCos would be good. Some kind
>> of communication with eCos is required I think, e.g. a
>> recommended way how to generate a regular interrupt so that if
>> some condition is detected in the FIQ handler a regular ISR
>> can overtake.
>
> I've done this before, but it used hardware support.
>
> The Intel StrongARM interrupt controller had a bit you could
> set to cause an IRQ interrupt to happen. So in the FIQ you hit
> this bit and exit the FIQ. Once interrupts are re-enabled the
> IRQ goes off and you are in normal eCos interrupt context.
How did eCos know where the interrupt came from? Did that bit
you set have it's own unique hardware-generated ID value?
> I don't know of a generic way to do this. There is no
> standardised interrupt controller for ARMs.
I think it's going to be target-dependent.
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