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--- Comment #11 from Ilija Kocho <[email protected]> 2012-01-11 20:32:34 GMT --- Hi Tomas, thank you for the update and here are my first notes: ISR priority Cortex-M NVIC implements priority arbitration with most significant /n/ bits implemented. Consequently in Kinetis (4 bits) they are bits 7..4 so priorities range 0x00, 0x10,..,0xf0. But this is not end of the story for eCos. Please visit this thread for full explanation (both references and follow-ups): http://ecos.sourceware.org/ml/ecos-devel/2010-11/msg00007.html It would be good to have configurable ISR priority. I understand that some drivers do not provide such control, but IMO that ISR priority manipulation may be important for tuning system behavior. And it is just a cdl per bus. I2C buses It would be good that unused buses are inactive - not present. Then user (or higher level I2C driver) activates the necessary bus by implementing respective interface. Also some parameters such as speed should be private to the bus. I can imagine two devices using separate buses at different speeds simultaneously. Also we don't need 2 init functions. Instead you can place parameters such as CYGHWR_IO_I2C_FREESCALE_I2Cx_PIN_SDA, etc. in the bus structure (or some const if you wish to save some RAM). Ilija -- Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.
