Revision: 14798
http://sourceforge.net/p/edk2/code/14798
Author: oliviermartin
Date: 2013-10-24 11:49:32 +0000 (Thu, 24 Oct 2013)
Log Message:
-----------
ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers
when Uniprocessor
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ
(Read as Zero).
So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <[email protected]>
Modified Paths:
--------------
trunk/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
Modified: trunk/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
===================================================================
--- trunk/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c 2013-10-23 05:35:07 UTC
(rev 14797)
+++ trunk/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c 2013-10-24 11:49:32 UTC
(rev 14798)
@@ -378,12 +378,12 @@
CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
This value
- // cannot be 0.
- ASSERT (CpuTarget != 0);
-
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index *
4), CpuTarget);
+ // is 0 when we run on a uniprocessor platform.
+ if (CpuTarget != 0) {
+ // The 8 first Interrupt Processor Targets Registers are read-only
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
+ MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index
* 4), CpuTarget);
+ }
}
// Set binary point reg to 0x7 (no preemption)
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