Revision: 17435
http://sourceforge.net/p/edk2/code/17435
Author: lersek
Date: 2015-05-13 09:31:49 +0000 (Wed, 13 May 2015)
Log Message:
-----------
OvmfPkg: consolidate POWER_MGMT_REGISTER_PIIX4() on "I440FxPiix4.h" macros
All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.
Cc: Gabriel Somlo <[email protected]>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <[email protected]>
Acked-by: Gabriel Somlo <[email protected]>
Tested-by: Gabriel Somlo <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Modified Paths:
--------------
trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
trunk/edk2/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
trunk/edk2/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
trunk/edk2/OvmfPkg/PlatformPei/Platform.c
Modified: trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
===================================================================
--- trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c 2015-05-13
09:31:44 UTC (rev 17434)
+++ trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c 2015-05-13
09:31:49 UTC (rev 17435)
@@ -22,7 +22,6 @@
// Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -58,9 +57,9 @@
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
Modified: trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
===================================================================
--- trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
2015-05-13 09:31:44 UTC (rev 17434)
+++ trunk/edk2/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
2015-05-13 09:31:49 UTC (rev 17435)
@@ -23,7 +23,6 @@
// Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -56,9 +55,9 @@
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
@@ -114,7 +113,7 @@
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
Modified: trunk/edk2/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
===================================================================
--- trunk/edk2/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c 2015-05-13
09:31:44 UTC (rev 17434)
+++ trunk/edk2/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c 2015-05-13
09:31:49 UTC (rev 17435)
@@ -61,7 +61,7 @@
HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
Modified: trunk/edk2/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
===================================================================
--- trunk/edk2/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c 2015-05-13
09:31:44 UTC (rev 17434)
+++ trunk/edk2/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c 2015-05-13
09:31:49 UTC (rev 17435)
@@ -860,7 +860,7 @@
mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (mHostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
//
// 00:01.0 ISA Bridge (PIIX4) LNK routing targets
//
Modified: trunk/edk2/OvmfPkg/PlatformPei/Platform.c
===================================================================
--- trunk/edk2/OvmfPkg/PlatformPei/Platform.c 2015-05-13 09:31:44 UTC (rev
17434)
+++ trunk/edk2/OvmfPkg/PlatformPei/Platform.c 2015-05-13 09:31:49 UTC (rev
17435)
@@ -252,9 +252,9 @@
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = BIT0; // PIIX4_PMIOSE
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
------------------------------------------------------------------------------
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