Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: c248802e40dc2cea007a7063b73feb0d04809261
https://github.com/tianocore/edk2/commit/c248802e40dc2cea007a7063b73feb0d04809261
Author: Patrick Rudolph <[email protected]>
Date: 2022-03-29 (Tue, 29 Mar 2022)
Changed paths:
M UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
Log Message:
-----------
UefiPayloadPkg: Fix PciHostBridgeLib
On modern platforms with TBT devices the coreboot resource allocator
opens large PCI bridge MMIO windows above 4GiB to place hotplugable
PCI BARs there as they won't fit below 4GiB. In addition modern
GPGPU devices have very big PCI bars that doesn't fit below 4GiB.
The PciHostBridgeLib made lots of assumptions about the coreboot
resource allocator that were not verified at runtime and are no
longer true.
Remove all of the 'coreboot specific' code and implement the same
logic as OvmfPkg's ScanForRootBridges.
Fixes assertion
"ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL".
Tested with coreboot as bootloader on platforms that have PCI resources
above 4GiB and on platforms that don't have resources above 4GiB.
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Guo Dong <[email protected]>
Reviewed-by: Maurice Ma <[email protected]>
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