Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 75e3c2435c7f10675d075ae7e5d4e9dea7331bcf
https://github.com/tianocore/edk2/commit/75e3c2435c7f10675d075ae7e5d4e9dea7331bcf
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
A UefiCpuPkg/Include/Library/CpuPageTableLib.h
A UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
A UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
A UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
A UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c
M UefiCpuPkg/UefiCpuPkg.dec
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs
The lib includes two APIs:
* PageTableMap
It creates/updates mapping from LA to PA.
The implementation only supports paging structures used in 64bit
mode now. PAE paging structure support will be added in future.
* PageTableParse
It parses the page table and returns the mapping relations in an
array of IA32_MAP_ENTRY.
It passed some stress tests. These test code will be upstreamed in
other patches following edk2 Unit Test framework.
Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: f336e30ba14f182836919a7662134ac28ded983a
https://github.com/tianocore/edk2/commit/f336e30ba14f182836919a7662134ac28ded983a
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
UefiCpuPkg/CpuPageTableLib: Return error on invalid parameters
When LinearAddress or Length is not aligned on 4KB, PageTableMap()
should return Invalid Parameter.
Signed-off-by: Zhiguang Liu <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: bf334513b3eb02ef98e5b38e0b7b5d7408492fdd
https://github.com/tianocore/edk2/commit/bf334513b3eb02ef98e5b38e0b7b5d7408492fdd
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask
To reproduce the issue:
UINTN PageTable;
VOID *Buffer;
UINTN PageTableBufferSize;
IA32_MAP_ATTRIBUTE Attribute;
IA32_MAP_ATTRIBUTE Mask;
RETURN_STATUS Status;
Attribute.Uint64 = 0;
Mask.Uint64 = 0;
PageTableBufferSize = 0;
PageTable = 0;
Buffer = NULL;
Attribute.Bits.Present = 1;
Attribute.Bits.Nx = 1;
Mask.Bits.Present = 1;
Mask.Uint64 = MAX_UINT64;
//
// Create page table to cover [0, 10M)
//
Status = PageTableMap (
&PageTable, PagingMode, Buffer, &PageTableBufferSize,
0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
);
ASSERT (Status == RETURN_BUFFER_TOO_SMALL);
Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
Status = PageTableMap (
&PageTable, PagingMode, Buffer, &PageTableBufferSize,
0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
);
ASSERT (Status == RETURN_SUCCESS);
//
// Change the mapping for [0, 4KB)
// No change actually. Just clear Nx bit in Mask.
//
Mask.Bits.Nx = 0;
PageTableBufferSize = 0;
Status = PageTableMap (
&PageTable, PagingMode, NULL, &PageTableBufferSize,
0, (UINT64)SIZE_4KB, &Attribute, &Mask
);
ASSERT (Status == RETURN_SUCCESS); // FAIL!!
The root cause is when comparing the existing mapping attributes
against the requested one, Mask is not used but it should be used.
Signed-off-by: Zhiguang Liu <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: 13a0471bfdcc1c7b18e182ca554d2ce98116e500
https://github.com/tianocore/edk2/commit/13a0471bfdcc1c7b18e182ca554d2ce98116e500
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Refactor the logic
The patch replaces
LinearAddress + Offset == RegionStart
with
((LinearAddress + Offset) & RegionMask) == 0
The replace should not cause any behavior change.
Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
because the lower "BitStart" bits of RegionStart are all-zero,
all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
Because all lower "BitStart" bits of RegionMask is all-one and
bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.
2. In following loops of the while, even RegionStart is increased
by RegionLength, the lower "BitStart" bits are still all-zero.
So the two expressions still semantically equal to each other.
Signed-off-by: Ray Ni <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: 9cb8974f06c6cc2545a66e696a58911122dec9fd
https://github.com/tianocore/edk2/commit/9cb8974f06c6cc2545a66e696a58911122dec9fd
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Split the page entry when LA is aligned but PA is not
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.
The patch fixes the bug.
Signed-off-by: Zhiguang Liu <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: c16f02f7764cba228d9c70b7985ff7276b6de4cc
https://github.com/tianocore/edk2/commit/c16f02f7764cba228d9c70b7985ff7276b6de4cc
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.
The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.
Signed-off-by: Ray Ni <[email protected]>
Signed-off-by: Zhiguang Liu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: f4c845e46b3fb18a84c3f8ecfc6f2d4025c2ede1
https://github.com/tianocore/edk2/commit/f4c845e46b3fb18a84c3f8ecfc6f2d4025c2ede1
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Fix parent attributes are not inherited properly
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.
The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.
E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.
Signed-off-by: Zhiguang Liu <[email protected]>
Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: 9f53fd4ba7ac4abe82365f310e0a4bcccc4448b3
https://github.com/tianocore/edk2/commit/9f53fd4ba7ac4abe82365f310e0a4bcccc4448b3
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as read-only, today's logic unnecessarily changes
the paging structure in 2 aspects:
1. When setting PageTableBaseAddress in the entry, the code clears
all attributes.
2. Even the ReadWrite bit in parent entry is not set, the code clears
the ReadWrite bit in the leaf entry.
First change is wrong. It should not change other attributes when
setting the PA.
Second change is unnecessary. Because the parent entry already
declares the whole region as read-only, there is no need to clear
ReadWrite bit in the leaf entry again.
Signed-off-by: Zhiguang Liu <[email protected]>
Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: 927113c83b4106aedf57fd1c8dc6dad5f1fe6a69
https://github.com/tianocore/edk2/commit/927113c83b4106aedf57fd1c8dc6dad5f1fe6a69
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: Fix bug that wrongly requires extra size for mapping
With following paging structure to map
[2M-4K, 2M] as P = 1, RW = 0,
[2M, 4M] as P = 1, RW = 1:
PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
-> PDE[1](RW = 1)
When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.
But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.
The change fixes the bug.
Signed-off-by: Ray Ni <[email protected]>
Signed-off-by: Zhiguang Liu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Commit: e9e2ecab2d931069d5f9afaae313e09d42bee6e9
https://github.com/tianocore/edk2/commit/e9e2ecab2d931069d5f9afaae313e09d42bee6e9
Author: Ray Ni <[email protected]>
Date: 2022-08-09 (Tue, 09 Aug 2022)
Changed paths:
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
M UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
Log Message:
-----------
CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally
The change doesn't change functionality behavior.
Signed-off-by: Ray Ni <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/f1688ec9dab6...e9e2ecab2d93
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