Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 7178047402c07d369a2a3a0b0e5118c5e3d90ddc
https://github.com/tianocore/edk2/commit/7178047402c07d369a2a3a0b0e5118c5e3d90ddc
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
M MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
Log Message:
-----------
MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: fbec9aec00c2cc10de439f2f0c3accb52488d32f
https://github.com/tianocore/edk2/commit/fbec9aec00c2cc10de439f2f0c3accb52488d32f
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M MdePkg/Include/Register/RiscV64/RiscVEncoding.h
Log Message:
-----------
MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>
Commit: a9fc9bb4666f8412ca5f1beb9e7e8cff63463861
https://github.com/tianocore/edk2/commit/a9fc9bb4666f8412ca5f1beb9e7e8cff63463861
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
Log Message:
-----------
OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: a8a72fc1fffad1102f00a5b7a1a5726501582949
https://github.com/tianocore/edk2/commit/a8a72fc1fffad1102f00a5b7a1a5726501582949
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M OvmfPkg/RiscVVirt/Sec/Platform.c
Log Message:
-----------
OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: 33d0a3cc926c39bf27e29b0f8c7ac0266504afe6
https://github.com/tianocore/edk2/commit/33d0a3cc926c39bf27e29b0f8c7ac0266504afe6
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
Log Message:
-----------
OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: cc13dcc57675695d51efe0d61d772155c601a35b
https://github.com/tianocore/edk2/commit/cc13dcc57675695d51efe0d61d772155c601a35b
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M OvmfPkg/RiscVVirt/Sec/Memory.c
Log Message:
-----------
OvmfPkg: RiscVVirt: Remove satp bare mode setting
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: f220dcbba86bfc1222180c61bbd31dd6023433db
https://github.com/tianocore/edk2/commit/f220dcbba86bfc1222180c61bbd31dd6023433db
Author: Tuan Phan <[email protected]>
Date: 2023-07-15 (Sat, 15 Jul 2023)
Changed paths:
M OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
M UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
M UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
M UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
A UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
A UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
A UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
A UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
M UefiCpuPkg/UefiCpuPkg.dec
M UefiCpuPkg/UefiCpuPkg.dsc
Log Message:
-----------
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/e674096accc8...f220dcbba86b
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