Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: f36e1ec1f0a5fd3be84913e09181d7813444b620
https://github.com/tianocore/edk2/commit/f36e1ec1f0a5fd3be84913e09181d7813444b620
Author: Gao Cheng <[email protected]>
Date: 2023-09-28 (Thu, 28 Sep 2023)
Changed paths:
M MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
M MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h
M MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
M MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c
M MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h
M MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
Log Message:
-----------
MdeModulePkg/Xhci: Skip size round up for TRB during address translation
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560
TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI
device/host memory address, it may exceed xHCI host memory pool and
cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate
whether to enforce 64byte size alignment and round up. For TRB case,
should set it to FALSE to skip the size round up.
Signed-off-by: Gao Cheng <[email protected]>
Cc: Hao A Wu <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Jian J Wang <[email protected]>
Cc: Liming Gao <[email protected]>
Reviewed-by: Hao A Wu <[email protected]>
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