Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 286b30f517ef35ae2764f13f077f0f120372a286
https://github.com/tianocore/edk2/commit/286b30f517ef35ae2764f13f077f0f120372a286
Author: Dhaval Sharma <[email protected]>
Date: 2023-12-19 (Tue, 19 Dec 2023)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
M MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
Log Message:
-----------
MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Pedro Falcato <[email protected]>
Signed-off-by: Dhaval Sharma <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Commit: 30faafd0247af0a6534caf2a6ac3231fa8e63d86
https://github.com/tianocore/edk2/commit/30faafd0247af0a6534caf2a6ac3231fa8e63d86
Author: Dhaval <[email protected]>
Date: 2023-12-19 (Tue, 19 Dec 2023)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
M MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
M MdePkg/Library/BaseLib/RiscV64/FlushCache.S
Log Message:
-----------
MdePkg: Rename Cache Management Function To Clarify Fence Based Op
There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Sunil V L <[email protected]>
Cc: Daniel Schaefer <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Pedro Falcato <[email protected]>
Signed-off-by: Dhaval Sharma <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Commit: 26727c2ae2a8883b7f4be23c26b6209ea763c816
https://github.com/tianocore/edk2/commit/26727c2ae2a8883b7f4be23c26b6209ea763c816
Author: Dhaval <[email protected]>
Date: 2023-12-19 (Tue, 19 Dec 2023)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
A MdePkg/Include/RiscV64/RiscVasm.inc
M MdePkg/Library/BaseLib/BaseLib.inf
R MdePkg/Library/BaseLib/RiscV64/FlushCache.S
A MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
Log Message:
-----------
MdePkg: Implement RISC-V Cache Management Operations
Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.
Notes:
1. CMO only supports block based Operations. Meaning cache
flush/invd/clean Operations are not available for the entire
range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
independent. binutils 2.39+ compilers support CMO instructions.
Test:
1. Ensured correct instructions are refelecting in asm
2. Qemu implements basic support for CMO operations in that it allwos
instructions without exceptions. Verified it works properly in
that sense.
3. SG2042Pkg implements CMO-like instructions. It was verified that
CpuFlushCpuDataCache works fine. This more of less
confirms that framework is alright.
4. TODO: Once Silicon is available with exact instructions, we will
further verify this.
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Sunil V L <[email protected]>
Cc: Daniel Schaefer <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Pedro Falcato <[email protected]>
Signed-off-by: Dhaval Sharma <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Reviewed-by: Sunil V L <sunilvl@...>
Reviewed-by: Jingyu Li <jingyu.li01@...>
Commit: 904b002c505cc689a2075745e1de529da5895c41
https://github.com/tianocore/edk2/commit/904b002c505cc689a2075745e1de529da5895c41
Author: Dhaval Sharma <[email protected]>
Date: 2023-12-19 (Tue, 19 Dec 2023)
Changed paths:
M MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
M MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
M MdePkg/MdePkg.dec
M MdePkg/MdePkg.uni
Log Message:
-----------
MdePkg: Utilize Cache Management Operations Implementation For RISC-V
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Pedro Falcato <[email protected]>
Signed-off-by: Dhaval Sharma <[email protected]>
Acked-by: Laszlo Ersek <[email protected]>
Reviewed-by: Pedro Falcato <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Commit: b1f33cbf8113bb07526c9f6946c250c7d9db44f9
https://github.com/tianocore/edk2/commit/b1f33cbf8113bb07526c9f6946c250c7d9db44f9
Author: Dhaval <[email protected]>
Date: 2023-12-19 (Tue, 19 Dec 2023)
Changed paths:
M OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
Log Message:
-----------
OvmfPkg/RiscVVirt: Override for RISC-V CPU Features
This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Sunil V L <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Pedro Falcato <[email protected]>
Signed-off-by: Dhaval Sharma <[email protected]>
Acked-by: Laszlo Ersek <[email protected]>
Reviewed-by: Andrei Warkentin <andrei.warkentin@...>
Reviewed-by: Sunil V L <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/3c66390e4a51...b1f33cbf8113
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