Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: fd629ef6e3dc894ddcfefe21542190f26c8c5c65
https://github.com/tianocore/edk2/commit/fd629ef6e3dc894ddcfefe21542190f26c8c5c65
Author: Sunil V L <[email protected]>
Date: 2024-01-11 (Thu, 11 Jan 2024)
Changed paths:
M MdePkg/MdePkg.dec
Log Message:
-----------
MdePkg.dec: RISC-V: Define override bit for Sstc extension
Define the BIT 1 as the override bit for Sstc extension. This will be
used by the timer driver to decide whether to use SBI calls or direct
CSR access to configure the timer.
Cc: Liming Gao <[email protected]>
Cc: Michael D Kinney <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Commit: 8ae17a71afc31410e50d86d008c2a7b9df1a7d22
https://github.com/tianocore/edk2/commit/8ae17a71afc31410e50d86d008c2a7b9df1a7d22
Author: Sunil V L <[email protected]>
Date: 2024-01-11 (Thu, 11 Jan 2024)
Changed paths:
M MdePkg/Include/Library/BaseLib.h
M MdePkg/Include/Register/RiscV64/RiscVEncoding.h
M MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
Log Message:
-----------
MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
stimecmp is a CSR supported only when Sstc extension is supported by the
platform. This register can be used to set the timer interrupt directly in
S-mode instead of going via SBI call. Add a function to update this
register.
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Commit: f91029947b748d16e07d7bc68e94ba6f5dcd528b
https://github.com/tianocore/edk2/commit/f91029947b748d16e07d7bc68e94ba6f5dcd528b
Author: Sunil V L <[email protected]>
Date: 2024-01-11 (Thu, 11 Jan 2024)
Changed paths:
M UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
M UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
M UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
Log Message:
-----------
UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
Sstc extension allows to program the timer and receive the interrupt
without using an SBI call. This reduces the latency to generate the timer
interrupt. So, detect whether Sstc extension is supported and use the
stimecmp register directly to program the timer interrupt.
Cc: Gerd Hoffmann <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Reviewed-by: Dhaval Sharma <[email protected]>
Commit: ebf378a1ada6d128dbf32aec76b3911895747bbb
https://github.com/tianocore/edk2/commit/ebf378a1ada6d128dbf32aec76b3911895747bbb
Author: Sunil V L <[email protected]>
Date: 2024-01-11 (Thu, 11 Jan 2024)
Changed paths:
M OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
Log Message:
-----------
OvmfPkg/RiscVVirt: Override Sstc extension
Override Sstc extension and use SBI calls itself by default for RISC-V
qemu virt platform.
Cc: Andrei Warkentin <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Reviewed-by: Andrei Warkentin <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/889535caf886...ebf378a1ada6
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