Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 7f1ffba5de3d9840dbeeba20fba165f2fb724941
https://github.com/tianocore/edk2/commit/7f1ffba5de3d9840dbeeba20fba165f2fb724941
Author: Dat Mach <[email protected]>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
M MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
Log Message:
-----------
MdeModulePkg/Xhci: Skip another size round up for TRB address
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560
Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the DXE_ASSERT
caused by the TRB size round up from 16 to 64 for most cases.
However, there is a remaining case that the TRB size is also rounded up
during setting TR dequeue pointer that would trigger DXE_ASSERT.
This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer to
fix this issue as well.
Cc: Gao Cheng <[email protected]>
Cc: Hao A Wu <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Liming Gao <[email protected]>
Signed-off-by: Dat Mach <[email protected]>
Reviewed-by: Gao Cheng <[email protected]>
Reviewed-by: Hao A Wu <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
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