Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: 303faa460c868184c0a4757e9de87ff8092c9e0f
https://github.com/tianocore/edk2/commit/303faa460c868184c0a4757e9de87ff8092c9e0f
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M MdePkg/Include/IndustryStandard/Acpi66.h
Log Message:
-----------
MdePkg: Acpi66: Add few more RISC-V definitions
Update the header with few more definitions for RISC-V released in ACPI
6.6 spec.
Signed-off-by: Sunil V L <[email protected]>
Commit: 89327d3fd1e6d0bd5a62e0c6dea52c87cdb75c15
https://github.com/tianocore/edk2/commit/89327d3fd1e6d0bd5a62e0c6dea52c87cdb75c15
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/Acpi/Common/AcpiSsdtPcieLib/SsdtPcieGenerator.c
Log Message:
-----------
DynamicTablesPkg/AcpiSsdtPcieLib: Restrict IRQ range check to ARM only
Modify the interrupt flags SPI range validation to apply only for ARM
architectures. This check ensures that interrupt flags are valid SPIs,
but it is ARM-specific and may cause false assertions on other
architectures.
By enabling this check exclusively for ARM, we avoid erroneous
assertions on non-ARM platforms.
Signed-off-by: Sunil V L <[email protected]>
Commit: f43f1f2f56fd398bd0dbd168edc7fb673d1895a2
https://github.com/tianocore/edk2/commit/f43f1f2f56fd398bd0dbd168edc7fb673d1895a2
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Include/ConfigurationManagerObject.h
A DynamicTablesPkg/Include/RiscVNameSpaceObjects.h
Log Message:
-----------
DynamicTablesPkg: Add RISC-V Namespace header
Add a new header file to define RISC-V Namespace objects used by the
Configuration Manager.
Include the new header in the main Configuration Manager Object header
to ensure the definitions are available where needed.
Signed-off-by: Sunil V L <[email protected]>
Commit: 8b4cca46da3373ab2dbd885ed31a77da33f69b5d
https://github.com/tianocore/edk2/commit/8b4cca46da3373ab2dbd885ed31a77da33f69b5d
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M
DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
Log Message:
-----------
DynamicTablesPkg/TableHelperLib: Add RISC-V structure parsers
Add support for parsing RISC-V-specific structures in TableHelperLib.
These parsers assist in interpreting and processing Configuration
Manager (CM) objects related to RISC-V hardware components.
Signed-off-by: Sunil V L <[email protected]>
Commit: ce5d42269186b526d68cdbbf928aae69e4aca240
https://github.com/tianocore/edk2/commit/ce5d42269186b526d68cdbbf928aae69e4aca240
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/CmObjectTokenFixer.c
M DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepo.c
M
DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepoInternal.h
Log Message:
-----------
DynamicTablesPkg: Update DynamicPlatRepo for RISC-V namespace
Update DynamicPlatRepo to incorporate the newly introduced RISC-V
namespace. This change ensures that platform repository data aligns
with RISC-V specific object definitions and structures.
Currently only ARM command objects are supported to fix up the self
token. However, some of the RISC-V command objects also need token
fixers. Add support for RISC-V token fixers.
This update is necessary to support RISC-V ACPI table generation and
platform configuration management.
Signed-off-by: Sunil V L <[email protected]>
Commit: 261e7715a1a302ad2b44d10d357a9ef456b9c7ee
https://github.com/tianocore/edk2/commit/261e7715a1a302ad2b44d10d357a9ef456b9c7ee
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
A
DynamicTablesPkg/Library/Acpi/Common/AcpiSsdtCpuTopologyLib/RiscV/RiscVSsdtCpuTopologyGenerator.c
M
DynamicTablesPkg/Library/Acpi/Common/AcpiSsdtCpuTopologyLib/SsdtCpuTopologyLib.inf
Log Message:
-----------
DynamicTablesPkg/AcpiSsdtCpuTopologyLib: Add RISC-V support
Add support for generating CPU topology information for RISC-V platforms
based on RINTC structures.
Signed-off-by: Sunil V L <[email protected]>
Commit: 7cd967bb6318a4203c13dd6345e8c2152c9c515e
https://github.com/tianocore/edk2/commit/7cd967bb6318a4203c13dd6345e8c2152c9c515e
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/Acpi/Common/AcpiFadtLib/AcpiFadtLib.inf
A
DynamicTablesPkg/Library/Acpi/Common/AcpiFadtLib/RiscV/RiscVFadtGenerator.c
Log Message:
-----------
DynamicTablesPkg/AcpiFadtLib: Add RISC-V support
Add support for generating the Fixed ACPI Description Table (FADT) for
RISC-V platforms using the common FADT generator.
Signed-off-by: Sunil V L <[email protected]>
Commit: 7b6ba9f31f7c5c3d6dcaed67babc2adba2147bd9
https://github.com/tianocore/edk2/commit/7b6ba9f31f7c5c3d6dcaed67babc2adba2147bd9
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/Acpi/Common/AcpiDbg2Lib/AcpiDbg2Lib.inf
A
DynamicTablesPkg/Library/Acpi/Common/AcpiDbg2Lib/RiscV/RiscVDbg2Generator.c
Log Message:
-----------
DynamicTablesPkg/AcpiDbg2Lib: Add RISC-V support
Add support for generating the ACPI DBG2 (Debug Port Table) for RISC-V
platforms.
Signed-off-by: Sunil V L <[email protected]>
Commit: 2ad2a4d07631598e187da3730df730516f977e24
https://github.com/tianocore/edk2/commit/2ad2a4d07631598e187da3730df730516f977e24
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/Acpi/Common/AcpiSratLib/AcpiSratLib.inf
A
DynamicTablesPkg/Library/Acpi/Common/AcpiSratLib/RiscV/RiscVSratGenerator.c
Log Message:
-----------
DynamicTablesPkg/AcpiSratLib: Add RISC-V support
Add support for generating the ACPI SRAT (System Resource Affinity Table)
for RISC-V platforms.
Signed-off-by: Sunil V L <[email protected]>
Commit: 58f59f60d68a961c733db1438834e01d6ab5513a
https://github.com/tianocore/edk2/commit/58f59f60d68a961c733db1438834e01d6ab5513a
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/DynamicTables.dsc.inc
Log Message:
-----------
DynamicTablesPkg: Add basic RISC-V support to DynamicTables.dsc.inc
Add initial support for RISC-V in DynamicTables.dsc.inc by including
common ACPI table generators required for RISC-V platforms.
This lays the groundwork for enabling RISC-V-specific dynamic table
generation in the platform firmware.
Signed-off-by: Sunil V L <[email protected]>
Commit: 36670a4bda6d50b1146c297ba9bf3f4e3be5333c
https://github.com/tianocore/edk2/commit/36670a4bda6d50b1146c297ba9bf3f4e3be5333c
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.inf
A
DynamicTablesPkg/Drivers/DynamicTableManagerDxe/RiscV/RiscVDynamicTableManagerDxe.c
Log Message:
-----------
DynamicTablesPkg/DynamicTableManagerDxe: Add RISC-V support
Add RISC-V-specific mAcpiVerifyTables entries to enable verification of
RISC-V ACPI tables during Dynamic Table Manager execution.
This ensures that RISC-V ACPI tables such as MADT, RHCT, and others are
properly validated and integrated at runtime.
Signed-off-by: Sunil V L <[email protected]>
Commit: 319114e477d72bc55d36267548344f66fbd24d89
https://github.com/tianocore/edk2/commit/319114e477d72bc55d36267548344f66fbd24d89
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/DynamicTables.dsc.inc
A DynamicTablesPkg/Library/Acpi/RiscV/AcpiMadtLibRiscV/AcpiMadtLibRiscV.inf
A DynamicTablesPkg/Library/Acpi/RiscV/AcpiMadtLibRiscV/MadtGenerator.c
Log Message:
-----------
DynamicTablesPkg/Acpi: Add MADT generator for RISC-V
Add a MADT (Multiple APIC Description Table) generator implementation
for RISC-V. RISC-V platforms may use one or more of the following
interrupt controllers: RINTC, IMSIC, PLIC, and APLIC.
This generator constructs the appropriate MADT entries for the
supported controllers and enables MADT generation for RISC-V platforms.
Signed-off-by: Sunil V L <[email protected]>
Commit: d612fd272f2680b28854fd18e51027fc1ac2628a
https://github.com/tianocore/edk2/commit/d612fd272f2680b28854fd18e51027fc1ac2628a
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/DynamicTables.dsc.inc
M DynamicTablesPkg/Include/AcpiTableGenerator.h
A DynamicTablesPkg/Library/Acpi/RiscV/AcpiRhctLibRiscV/AcpiRhctLibRiscV.inf
A DynamicTablesPkg/Library/Acpi/RiscV/AcpiRhctLibRiscV/RhctGenerator.c
A DynamicTablesPkg/Library/Acpi/RiscV/AcpiRhctLibRiscV/RhctGenerator.h
Log Message:
-----------
DynamicTablesPkg/Acpi: Add RHCT generator for RISC-V
Add a generator for the RISC-V Hart Capabilities Table (RHCT), a new
ACPI table used to convey CPU feature information to the operating
system.
This generator enables firmware to describe RISC-V hart capabilities
in a standardized way as part of the ACPI table set.
Signed-off-by: Sunil V L <[email protected]>
Commit: 3a026170a48d72c3da2a5ff736f5dd1855fd0666
https://github.com/tianocore/edk2/commit/3a026170a48d72c3da2a5ff736f5dd1855fd0666
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/DynamicTables.dsc.inc
M DynamicTablesPkg/Include/AcpiTableGenerator.h
A
DynamicTablesPkg/Library/Acpi/RiscV/AcpiSsdtPlicAplicLib/AcpiSsdtPlicAplicLib.inf
A
DynamicTablesPkg/Library/Acpi/RiscV/AcpiSsdtPlicAplicLib/SsdtPlicAplicGenerator.c
Log Message:
-----------
DynamicTablesPkg/RISC-V: Add AcpiSsdtPlicAplicLib library
Add AcpiSsdtPlicAplicLib to create PLIC and APLIC device entries in the
RISC-V namespace. These interrupt controller devices are essential for
accurate ACPI namespace representation on RISC-V platforms.
This library facilitates SSDT generation for PLIC and APLIC, enabling
proper OS discovery and configuration.
Signed-off-by: Sunil V L <[email protected]>
Commit: b6c60927c45ff311b3adc6a6c44a3628c5f7a062
https://github.com/tianocore/edk2/commit/b6c60927c45ff311b3adc6a6c44a3628c5f7a062
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParserLib.inf
M DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtUtility.h
A
DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/HartInfo/RiscVTimerDispatcher.c
A
DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/HartInfo/RiscVTimerDispatcher.h
A DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/Intc/RiscVExtIntcData.c
A DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/Intc/RiscVIntcParser.c
A DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/Intc/RiscVIntcParser.h
A DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/RiscVFdtHwInfoParser.c
A DynamicTablesPkg/Library/FdtHwInfoParserLib/RiscV/RiscVFdtInterrupt.c
Log Message:
-----------
DynamicTablesPkg/FdtHwInfoParserLib: Add RISC-V FDT parsers
Add FDT parsers for RISC-V that extract hardware information from the
Flattened Device Tree (FDT) and create corresponding Configuration
Manager (CM) objects.
These CM objects provide the necessary data for ACPI table generators,
such as MADT, RHCT, and SSDT, to construct RISC-V-specific tables.
Signed-off-by: Sunil V L <[email protected]>
Commit: 0411b05771e58719b94e09e51c1d0ae8a263b3b4
https://github.com/tianocore/edk2/commit/0411b05771e58719b94e09e51c1d0ae8a263b3b4
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/FdtHwInfoParserLib/Pci/PciConfigSpaceParser.c
Log Message:
-----------
DynamicTablesPkg/FdtHwInfoParserLib: Detect IRQ type based on IntcCells
For some architectures and interrupt controllers, such as RISC-V’s
PLIC, the PCI interrupt map does not include an explicit IRQ type.
Update the parser to set the IRQ type to 0 when the interrupt
controller’s 'interrupt-cells' property has a count of 1 or less,
indicating no IRQ type information is provided.
This change improves compatibility with RISC-V and similar platforms.
Signed-off-by: Sunil V L <[email protected]>
Commit: 524e4c8a0586ef7ea874300c63a8fd8335bdafe3
https://github.com/tianocore/edk2/commit/524e4c8a0586ef7ea874300c63a8fd8335bdafe3
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/FdtHwInfoParserLib/Pci/PciConfigSpaceParser.c
Log Message:
-----------
DynamicTablesPkg/FdtHwInfoParserLib/Pci: Convert IRQ to GSI for RISC-V
On RISC-V platforms, the Global System Interrupt (GSI) space is divided
across multiple PLIC/APLIC interrupt controllers. The IRQ number in the
device tree (DT) needs to be translated to the corresponding GSI by:
1. Mapping the IRQ number to its parent interrupt controller using the
phandle from the 'interrupt-map' property.
2. Converting the IRQ to a GSI number using the interrupt controller’s
GSI base.
This change ensures accurate IRQ-to-GSI translation for PCI devices,
enabling correct interrupt routing on RISC-V systems.
Signed-off-by: Sunil V L <[email protected]>
Commit: d6748c514b1f04ecf4e4ed71bb41a159462cde77
https://github.com/tianocore/edk2/commit/d6748c514b1f04ecf4e4ed71bb41a159462cde77
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/Library/FdtHwInfoParserLib/Serial/SerialPortParser.c
Log Message:
-----------
DynamicTablesPkg/FdtHwInfoParserLib/Serial: RISC-V: Convert to GSI
In RISC-V, the GSI space is spread across multiple PLICs/APLICs. Hence,
any device's IRQ number in the FDT should be appropriately converted to
a GSI number based on its parent interrupt controller. Do this for UART
parsing in RISC-V.
Signed-off-by: Sunil V L <[email protected]>
Commit: 8b3b2a64886f6ce6a987421668d1beb8ddff1e49
https://github.com/tianocore/edk2/commit/8b3b2a64886f6ce6a987421668d1beb8ddff1e49
Author: Sunil V L <[email protected]>
Date: 2025-12-02 (Tue, 02 Dec 2025)
Changed paths:
M DynamicTablesPkg/DynamicTablesPkg.ci.yaml
Log Message:
-----------
DynamicTablesPkg: Add RISC-V terms to spell check ignore list
Update the spell check ignore list to include RISC-V specific words
and terminology. This prevents false-positive spelling errors for
RISC-V related terms during automated checks.
Signed-off-by: Sunil V L <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/ede299f2413d...8b3b2a64886f
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