Branch: refs/heads/master
  Home:   https://github.com/tianocore/edk2
  Commit: 21b358b81d8fd9d9b9a09a344bace41c13017d37
      
https://github.com/tianocore/edk2/commit/21b358b81d8fd9d9b9a09a344bace41c13017d37
  Author: Vincent Gatine <[email protected]>
  Date:   2026-07-17 (Fri, 17 Jul 2026)

  Changed paths:
    M ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c

  Log Message:
  -----------
  ShellPkg/Pci: Restore BAR informations

Restore informations lost in the pci shell command.

sbsa-ref Host Bridge:

```
 Cache Line Size(C): 00                 Latency Timer(D): 00
 Header Type(0E):    00, Single function, PCI device
 Class: Bridge Device - Host/PCI bridge -
+Base Address Registers(10):
+  (None)
+Expansion ROM Disabled(30)
+
+Cardbus CIS ptr(28):   00000000
+Sub VendorID(2C):          1AF4      Subsystem ID(2E):      1100
+Capabilities Ptr(34):        00
+Interrupt Line(3C):          FF      Interrupt Pin(3D):       00
+Min_Gnt(3E):                 00      Max_Lat(3F):             00
```
sbsa-ref Ethernet Controller:

```
 Cache Line Size(C): 00                 Latency Timer(D): 00
 Header Type(0E):    00, Single function, PCI device
 Class: Network Controller - Ethernet controller -
+Base Address Registers(10):
+     Start_Address  Type  Space    Prefetchable?     Size             Limit
+  --------------------------------------------------------------------------
+          81060000  Mem   32 bits  No             00020000          8107FFFF
+          81040000  Mem   32 bits  No             00020000          8105FFFF
+              0000  I/O                               0020              001F
+          81080000  Mem   32 bits  No             00004000          81083FFF
+  --------------------------------------------------------------------------
+Expansion ROM Disabled(30)
+
+Cardbus CIS ptr(28):   00000000
+Sub VendorID(2C):          8086      Subsystem ID(2E):      0000
+Capabilities Ptr(34):        C8
+Interrupt Line(3C):          FF      Interrupt Pin(3D):       01
+Min_Gnt(3E):                 00      Max_Lat(3F):             00

 Pci Express device capability structure:
 CapID( 0):          10            NextCap Ptr( 1):    A0
```

Signed-off-by: Vincent Gatine <[email protected]>



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