The logic we have in place for i440fx does not work reliably on q35. For
example, if the guest has 2GB of RAM, we allow the PCI root bridge driver
to allocate the legacy video RAM BAR from the [2048 MB, 2816 MB] range,
which falls strictly outside of the Q35 PCI host MMIO aperture that QEMU
configures, and advertizes in ACPI.
In turn, PCI BARs that exist outside of the PCI host aperture that is
exposed in ACPI break Windows guests.
Allocating PCI MMIO resources at or above 3GB on Q35 ensures that we stay
within QEMU's aperture. (See the "w32.begin" assignments in
"hw/pci-host/q35.c".) Furthermore, in pc_q35_init() (file
"hw/i386/pc_q35.c"), QEMU ensures that the low RAM never "leaks" above
3GB.
The i440fx logic is left unchanged.
The Windows guest malfunction on Q35 was reported by Jon Panozzo of Lime
Technology, Inc.
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Igor Mammedov <imamm...@redhat.com>
Cc: Jon Panozzo <j...@lime-technology.com>
Cc: "Gabriel L. Somlo" <so...@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <ler...@redhat.com>
---
OvmfPkg/PlatformPei/Platform.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 9970d14..f6e2188 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -204,7 +204,20 @@ MemMapInitialization (
if (!mXen) {
UINT32 TopOfLowRam;
+ UINT32 PciBase;
+
TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ //
+ // A 3GB base will always fall into Q35's 32-bit PCI host aperture,
+ // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets
+ // the RAM below 4 GB exceed it.
+ //
+ PciBase = BASE_2GB + BASE_1GB;
+ ASSERT (TopOfLowRam <= PciBase);
+ } else {
+ PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
+ }
//
// address purpose size
@@ -219,8 +232,7 @@ MemMapInitialization (
// 0xFED20000 gap 896 KB
// 0xFEE00000 LAPIC 1 MB
//
- AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
- BASE_2GB : TopOfLowRam, 0xFC000000);
+ AddIoMemoryRangeHob (PciBase, 0xFC000000);
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
--
1.8.3.1
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