On 10/13/15 18:35, Brian J. Johnson wrote: > On 10/13/2015 08:26 AM, Laszlo Ersek wrote: >> >> First of all, if the edk2 reference code (in the SMM core and in >> PiSmmCpuDxeSmm) depends on such behavior justifiedly, then I think we >> have a bug in the PI specification. Namely, version 1.4 thereof does not >> seem to require that EFI_SMM_CONTROL2_PROTOCOL.Trigger() raise an SMI on >> *all* processors. (See volume 4, section 5.4.) >> >> In particular, the EFI_SMM_CONTROL2_PROTOCOL.Trigger() specification >> makes many references to SMI handling and dispatching. But I cannot make >> a mental connection between an SMI "broadcast", and "handling and >> dispatching" in edk2, since all "handling and dispatching" code in edk2 >> that is exposed via protocols, is non-reentrant with regard to multiple >> VCPUs, to my knowledge. >> >> One could argue that whatever code handles the SMI on the BP is >> responsible for bringing the APs into SMM as well, before doing any >> sensitive work. I'm not sure. > > Traditionally, SMI handling has been global. If the h/w didn't > broadcast the SMI to all CPUs, the SMI handler did so itself. The BSP > would wait for all APs to "check in" to SMM, then it would do whatever > work the SMI required, and signal the APs to resume. That ensured that > the OS wasn't active on the machine while the BSP was handling the SMI, > which was required for certain uses of SMI. > > However, this (obviously) doesn't scale well, so Intel has been moving > towards signaling SMI to only a single processor, and avoiding the > machine-wide rendezvous when it isn't necessary. BIOS implementations > may be lagging behind.
But... when is it necessary? Paolo implied it might not be necessary for us because MTRR changes are not relevant on our virtual platform -- otherwise all CPUs would have to agree on the MTRR settings --, but isn't there a security aspect to it as well? All UefiCpuPkg/UefiCpuPkg.dec says is: ## Indicates the CPU synchronization method used when processing an SMI. # 0x00 - Traditional CPU synchronization method.<BR> # 0x01 - Relaxed CPU synchronization method.<BR> # @Prompt SMM CPU Synchronization Method. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014 Uhm. Thanks?... > >> >> Second, if writing to ioport 0xb2 should *automatically* raise an SMI on >> all processors, then the QEMU code could be incorrect. However I could >> never derive such an "imperative" from the ICH9 spec. > > I too am having a hard time finding a clear statement of whether or not > ioport 0xb2 should *automatically* raise an SMI on all processors. Maybe > it's platform-specific? Something should state "it's platform-specific" then :) Thank you! Laszlo _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
