There is no need to issue a full data synchronization barrier and an instruction synchronization barrier after each and every set/way or MVA cache maintenance operation. So remove them.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> --- ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index bdede48724e6..aaccd38dc998 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -66,43 +66,31 @@ GCC_ASM_EXPORT (ArmReadCurrentEL) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): dc ivac, x0 // Invalidate single data cache line - dsb sy - isb ret ASM_PFX(ArmCleanDataCacheEntryByMVA): dc cvac, x0 // Clean single data cache line - dsb sy - isb ret ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): dc civac, x0 // Clean and invalidate single data cache line - dsb sy - isb ret ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): dc isw, x0 // Invalidate this line - dsb sy - isb ret ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): dc cisw, x0 // Clean and Invalidate this line - dsb sy - isb ret ASM_PFX(ArmCleanDataCacheEntryBySetWay): dc csw, x0 // Clean this line - dsb sy - isb ret -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
