On 11/27/15 16:23, jiewen yao wrote: > This series patch enables write protection in SMM. > We always set RW+P bit for page table by default, and set WP in CR0. > So that we can use page table write-protection for code later. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: "Yao, Jiewen" <jiewen....@intel.com> > Signed-off-by: "Paolo Bonzini" <pbonz...@redhat.com> > Suggested-by: "Kinney, Michael D" <michael.d.kin...@intel.com> > Tested-by: "Laszlo Ersek" <ler...@redhat.com> > Reviewed-by: "Kinney, Michael D" <michael.d.kin...@intel.com> > Cc: "Fan, Jeff" <jeff....@intel.com> > Cc: "Kinney, Michael D" <michael.d.kin...@intel.com> > Cc: "Laszlo Ersek" <ler...@redhat.com> > Cc: "Paolo Bonzini" <pbonz...@redhat.com> > > jiewen yao (2): > UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default. > UefiCpuPkg/PiSmmCpu: Always set WP in CR0. > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 14 ++++++++------ > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 13 ++++++++++++- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 12 ++++++------ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 8 ++++---- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 14 +++++++------- > 11 files changed, 43 insertions(+), 30 deletions(-) >
I very slightly cleaned up the commit messages, and committed the series to SVN, revisions 19067 and 19068. Thanks! Laszlo _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
