On Tue, Dec 08, 2015 at 04:19:47PM +0100, Ard Biesheuvel wrote: > On 8 December 2015 at 14:05, Cohen, Eugene <eug...@hp.com> wrote: > > Reviewed-by: Eugene Cohen <eug...@hp.com> > > > > Thanks Eugene > > @Leif: any concerns?
None - just stuck in a meeting :) Thanks. Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org> > >> -----Original Message----- > >> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] > >> Sent: Monday, December 07, 2015 12:06 AM > >> To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Cohen, Eugene > >> <eug...@hp.com> > >> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> > >> Subject: [PATCH] ArmPkg: update InvalidateInstructionCacheRange to > >> flush only to PoU > >> > >> From: "Cohen, Eugene" <eug...@hp.com> > >> > >> This patch updates the ArmPkg variant of > >> InvalidateInstructionCacheRange to > >> flush the data cache only to the point of unification (PoU). This > >> improves > >> performance and also allows invalidation in scenarios where it would > >> be > >> inappropriate to flush to the point of coherency (like when executing > >> code > >> from L2 configured as cache-as-ram). > >> > >> Contributed-under: TianoCore Contribution Agreement 1.0 > >> Signed-off-by: Eugene Cohen <eug...@hp.com> > >> > >> Added AARCH64 and ARM/GCC implementations of the above. > >> > >> Contributed-under: TianoCore Contribution Agreement 1.0 > >> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> > >> --- > >> ArmPkg/Include/Library/ArmLib.h | 8 > >> +++++++- > >> > >> ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib > >> .c | 2 +- > >> ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 6 > >> ++++++ > >> ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 6 > >> ++++++ > >> ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 5 > >> +++++ > >> 5 files changed, 25 insertions(+), 2 deletions(-) > >> > >> diff --git a/ArmPkg/Include/Library/ArmLib.h > >> b/ArmPkg/Include/Library/ArmLib.h > >> index 9622444ec63f..85fa1f600ba9 100644 > >> --- a/ArmPkg/Include/Library/ArmLib.h > >> +++ b/ArmPkg/Include/Library/ArmLib.h > >> @@ -183,12 +183,18 @@ ArmInvalidateDataCacheEntryByMVA ( > >> > >> VOID > >> EFIAPI > >> -ArmCleanDataCacheEntryByMVA ( > >> +ArmCleanDataCacheEntryToPoUByMVA( > >> IN UINTN Address > >> ); > >> > >> VOID > >> EFIAPI > >> +ArmCleanDataCacheEntryByMVA( > >> +IN UINTN Address > >> +); > >> + > >> +VOID > >> +EFIAPI > >> ArmCleanInvalidateDataCacheEntryByMVA ( > >> IN UINTN Address > >> ); > >> diff --git > >> a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceL > >> ib.c > >> b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceL > >> ib.c > >> index feab4497ac1b..1045f9068f4d 100644 > >> --- > >> a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceL > >> ib.c > >> +++ > >> b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceL > >> ib.c > >> @@ -64,7 +64,7 @@ InvalidateInstructionCacheRange ( > >> IN UINTN Length > >> ) > >> { > >> - CacheRangeOperation (Address, Length, > >> ArmCleanDataCacheEntryByMVA); > >> + CacheRangeOperation (Address, Length, > >> ArmCleanDataCacheEntryToPoUByMVA); > >> ArmInvalidateInstructionCache (); > >> return Address; > >> } > >> diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > >> b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > >> index c530d19e897e..db21f73f0ed7 100644 > >> --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > >> +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > >> @@ -22,6 +22,7 @@ > >> GCC_ASM_EXPORT (ArmInvalidateInstructionCache) > >> GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) > >> GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) > >> +GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA) > >> GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) > >> GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) > >> GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) > >> @@ -72,6 +73,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA): > >> ret > >> > >> > >> +ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): > >> + dc cvau, x0 // Clean single data cache line to PoU > >> + ret > >> + > >> + > >> ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): > >> dc civac, x0 // Clean and invalidate single data cache line > >> ret > >> diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S > >> b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S > >> index 5f030d92de31..7de1b11ef818 100644 > >> --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S > >> +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S > >> @@ -19,6 +19,7 @@ > >> GCC_ASM_EXPORT (ArmInvalidateInstructionCache) > >> GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) > >> GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) > >> +GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA) > >> GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) > >> GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) > >> GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) > >> @@ -69,6 +70,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA): > >> bx lr > >> > >> > >> +ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): > >> + mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU > >> + bx lr > >> + > >> + > >> ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): > >> mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache > >> line > >> bx lr > >> diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm > >> b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm > >> index df7e22dca2d9..a460bd2da7a9 100644 > >> --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm > >> +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm > >> @@ -34,6 +34,11 @@ CTRL_I_BIT EQU (1 << 12) > >> bx lr > >> > >> > >> + RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA > >> + mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU > >> + bx lr > >> + > >> + > >> RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA > >> mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data > >> cache line > >> bx lr > >> -- > >> 1.9.1 > > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
