The expression that was used to set it had no side effects.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Kelly Steele <kelly.ste...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <ler...@redhat.com>
---
QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c
b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c
index 26c56e603762..50692fea1f71 100644
--- a/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c
+++ b/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c
@@ -391,7 +391,7 @@ static void prog_ddr_timing_control(
MRCParams_t *mrc_params)
{
uint8_t TCL, WL;
- uint8_t TRP, TRCD, TRAS, TRFC, TWR, TWTR, TRRD, TRTP, TFAW;
+ uint8_t TRP, TRCD, TRAS, TWR, TWTR, TRRD, TRTP, TFAW;
uint32_t TCK;
RegDTR0 Dtr0;
@@ -416,7 +416,6 @@ static void prog_ddr_timing_control(
TRP = TCL; // Per CAT MRC
TRCD = TCL; // Per CAT MRC
TRAS = MCEIL(mrc_params->params.tRAS, TCK);
- TRFC = MCEIL(tRFC[mrc_params->params.DENSITY], TCK);
TWR = MCEIL(15000, TCK); // Per JEDEC: tWR=15000ps DDR2/3 from 800-1600
TWTR = MCEIL(mrc_params->params.tWTR, TCK);
--
1.8.3.1
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
