On 24 March 2016 at 21:30, Leo Duran <leo.du...@amd.com> wrote:
> From: Leendert van Doorn <leend...@paramecium.org>
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.du...@amd.com>
Hi Leo,
Thanks for the patches. I will respond to the patches individually
when appropriate, but I have some general comments as well.
- All the patches are authored by Leendert, but not using his AMD
address, and his sign off is missing, which looks a bit odd. In
general, it does make perfect sense for the person doing the
upstreaming (you) to add the sign off, basically stating that AMD is
able to release this under the Tianocore license, regardless of who
authored it. But it looks odd if the actual author is not identifiable
as an AMD engineer.
- When you use 'git send-email', you can pass all patch files at one,
that way, you will get a nice threaded series with numbers, i.e., 1/x
2/x etc
> ---
> ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
> b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
> index 135bd6b..3d39acd 100644
> --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
> +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
> @@ -40,12 +40,15 @@ ArmCpuSetup (
> }
>
> //
> - // If CPU is CortexA57 r0p0 apply Errata: 806969
> + // If CPU is CortexA57 r0p0 apply Errata workarounds
> //
> if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
> ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
> - // DisableLoadStoreWB
> - ArmSetCpuActlrBit (1ULL << 49);
> +
> + // Errata 806969: DisableLoadStoreWB (1ULL << 49)
> + // Errata 813420: Execute Data Cache clean as Data Cache
> clean/invalidate (1ULL << 44)
> + // Errata 814670: disable DMB nullification (1ULL << 58)
> + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
> }
> }
>
> --
> 1.9.1
>
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