Hi,

Has anyone tested Intel E1000 driver with 64-bit Physical address space?
Does it support?

Regards,
Shaveta

From: Shaveta Leekha
Sent: Monday, March 28, 2016 1:00 PM
To: edk2-devel@lists.01.org
Subject: PCIe memory transaction issue

Hi,

In PCIe memory transactions, I am facing an issue.

The scenario is:
Case 1:
In our system, we have allocated 32 bit memory space to one of the PCI device 
(E1000 NIC card) during enumeration and BAR programming.
When NIC card is getting used to transmit a ping packet, a local buffer is 
getting allocated from 32 bit main memory space.
In this case, the packet is getting sent out successfully.


Case 2:
Now when NIC card is getting used to transmit a ping packet, if a local buffer 
is allocated from 64 bit main memory space.
The packet failed to transmit out.

Doubt 1: Would it be possible for this PCI device/NIC card (in our case) to 
access this 64 bit address space for sending this packet out of system?
Doubt 2: If a device is allocated 32 bit Memory mapped space from 32 bit memory 
area, then for packet transactions, can we use 64 bit memory space?

Thanks and Regards,
Shaveta


Resource MAP for PCI bridge and one PCI device on bus 1 is:

PciBus: Resource Map for Root Bridge PciRoot(0x0)
Type =   Io16; Base = 0x0;      Length = 0x1000;        Alignment = 0xFFF
Base = 0x0;    Length = 0x1000;        Alignment = 0xFFF;      Owner = PPB  
[00|00|00:**]
Type =  Mem32; Base = 0x78000000;       Length = 0x5100000;     Alignment = 
0x3FFFFFF
Base = 0x78000000;     Length = 0x4000000;     Alignment = 0x3FFFFFF;  Owner = 
PPB  [00|00|00:14]
Base = 0x7C000000;     Length = 0x1000000;     Alignment = 0xFFFFFF;   Owner = 
PPB  [00|00|00:10]
Base = 0x7D000000;     Length = 0x100000;      Alignment = 0xFFFFF;    Owner = 
PPB  [00|00|00:**]

PciBus: Resource Map for Bridge [00|00|00]
Type =   Io16; Base = 0x0;      Length = 0x1000;        Alignment = 0xFFF
Base = 0x0;    Length = 0x20;  Alignment = 0x1F;       Owner = PCI  
[01|00|00:18]
Type =  Mem32; Base = 0x78000000;       Length = 0x4000000;     Alignment = 
0x3FFFFFF

gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x40000000
  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x40000000      # 128M
  gArmPlatformTokenSpaceGuid.PcdPciMemTranslation|0x1400000000
  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x1440000000
  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x40000000

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