Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/Include/Coreboot.h | 3 ++
CorebootModulePkg/Include/Library/CbParseLib.h | 12 ++++--
CorebootModulePkg/Library/CbParseLib/CbParseLib.c | 42 ++++++++++++++------
.../Library/PlatformBdsLib/BdsPlatform.c | 7 +++-
.../Library/PlatformBdsLib/PlatformBdsLib.inf | 6 +++
.../Library/PlatformHookLib/PlatformHookLib.c | 46 +++++++++++++++++++++-
.../Library/PlatformHookLib/PlatformHookLib.inf | 11 ++++--
7 files changed, 107 insertions(+), 20 deletions(-)
diff --git a/CorebootModulePkg/Include/Coreboot.h
b/CorebootModulePkg/Include/Coreboot.h
index f2f18be..74109b6 100644
--- a/CorebootModulePkg/Include/Coreboot.h
+++ b/CorebootModulePkg/Include/Coreboot.h
@@ -165,6 +165,9 @@ struct cb_serial {
UINT32 type;
UINT32 baseaddr;
UINT32 baud;
+ UINT32 regwidth;
+ UINT32 input_hertz;
+ UINT32 id;
};
#define CB_TAG_CONSOLE 0x00010
diff --git a/CorebootModulePkg/Include/Library/CbParseLib.h
b/CorebootModulePkg/Include/Library/CbParseLib.h
index 170375b..3243a16 100644
--- a/CorebootModulePkg/Include/Library/CbParseLib.h
+++ b/CorebootModulePkg/Include/Library/CbParseLib.h
@@ -113,7 +113,10 @@ CbParseFadtInfo (
@param pRegBase Pointer to the base address of serial port
registers
@param pRegAccessType Pointer to the access type of serial port
registers
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
+ @param pInputHertz Pointer to the input clock frequency
+ @param pId Pointer to the serial port ID
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
@@ -121,9 +124,12 @@ CbParseFadtInfo (
**/
RETURN_STATUS
CbParseSerialInfo (
- IN UINT32* pRegBase,
- IN UINT32* pRegAccessType,
- IN UINT32* pBaudrate
+ OUT UINT32 *pRegBase,
+ OUT UINT32 *pRegAccessType,
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pId
);
/**
diff --git a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
index 377abf3..962bcf5 100644
--- a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
+++ b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
@@ -216,8 +216,8 @@ FindCbMemTable (
*pMemTableSize = Entries[Idx].size;
}
- DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
- TableId, *pMemTable, Entries[Idx].size));
+ DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
+ TableId, *pMemTable, Entries[Idx].size));
return RETURN_SUCCESS;
}
}
@@ -479,15 +479,15 @@ CbParseFadtInfo (
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));
}
- //
- // Verify values for proper operation
- //
- ASSERT(Fadt->Pm1aCntBlk != 0);
- ASSERT(Fadt->PmTmrBlk != 0);
- ASSERT(Fadt->ResetReg.Address != 0);
- ASSERT(Fadt->Pm1aEvtBlk != 0);
- ASSERT(Fadt->Gpe0Blk != 0);
-
+ //
+ // Verify values for proper operation
+ //
+ ASSERT(Fadt->Pm1aCntBlk != 0);
+ ASSERT(Fadt->PmTmrBlk != 0);
+ ASSERT(Fadt->ResetReg.Address != 0);
+ ASSERT(Fadt->Pm1aEvtBlk != 0);
+ ASSERT(Fadt->Gpe0Blk != 0);
+
return RETURN_SUCCESS;
}
}
@@ -541,7 +541,10 @@ CbParseFadtInfo (
@param pRegBase Pointer to the base address of serial port
registers
@param pRegAccessType Pointer to the access type of serial port
registers
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
+ @param pInputHertz Pointer to the input clock frequency
+ @param pId Pointer to the serial port ID
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
@@ -551,7 +554,10 @@ RETURN_STATUS
CbParseSerialInfo (
OUT UINT32 *pRegBase,
OUT UINT32 *pRegAccessType,
- OUT UINT32 *pBaudrate
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pId
)
{
struct cb_serial *CbSerial;
@@ -569,6 +575,10 @@ CbParseSerialInfo (
*pRegBase = CbSerial->baseaddr;
}
+ if (pRegWidth != NULL) {
+ *pRegWidth = CbSerial->regwidth;
+ }
+
if (pRegAccessType != NULL) {
*pRegAccessType = CbSerial->type;
}
@@ -577,6 +587,14 @@ CbParseSerialInfo (
*pBaudrate = CbSerial->baud;
}
+ if (pInputHertz != NULL) {
+ *pInputHertz = CbSerial->input_hertz;
+ }
+
+ if (pId != NULL) {
+ *pId = CbSerial->id;
+ }
+
return RETURN_SUCCESS;
}
diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
index ef6a1b2..ed1b537 100644
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -78,6 +78,10 @@ PlatformBdsInit (
VOID
)
{
+ gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
+ gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
+ gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);
+ gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
}
@@ -121,7 +125,7 @@ Returns:
//
// Register COM1
//
- DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL,
(EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);
+ DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL,
(EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL
*)&gUartDeviceNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL
*)&gTerminalTypeDeviceNode);
@@ -786,6 +790,7 @@ PlatformBdsPolicyBehavior (
DEBUG ((EFI_D_INFO, "PlatformBdsPolicyBehavior\n"));
+ PlatformBdsInit();
ConnectRootBridge ();
//
diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
index 9c10272..e02c799 100644
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
+++ b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
@@ -45,6 +45,12 @@
DebugLib
PcdLib
GenericBdsLib
+ PlatformHookLib
+
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
index 8449997..96bf792 100644
--- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -18,6 +18,18 @@
#include <Library/CbParseLib.h>
#include <Library/PcdLib.h>
+typedef struct {
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The
value 0xFFFF terminates the list of entries.
+ UINT16 DeviceId; ///< Device ID to match the PCI device
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock
rate of 1843200 Hz
+ UINT64 Offset; ///< The byte offset into to the BAR
+ UINT8 BarIndex; ///< Which BAR to get the UART base address
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for
default register stride of 1 byte.
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0
for a default FIFO depth of 16 bytes.
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0
for a default FIFO depth of 16 bytes.
+ UINT8 Reserved[2];
+} PCI_SERIAL_PARAMETER;
+
/**
Performs platform specific initialization required for the CPU to access
the hardware associated with a SerialPortLib instance. This function does
@@ -38,8 +50,14 @@ PlatformHookSerialPortInitialize (
RETURN_STATUS Status;
UINT32 SerialRegBase;
UINT32 SerialRegAccessType;
+ UINT32 BaudRate;
+ UINT32 RegWidth;
+ UINT32 InputHertz;
+ UINT32 Id;
+ PCI_SERIAL_PARAMETER *SerialParam;
- Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, NULL);
+ Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType,
+ &RegWidth, &BaudRate, &InputHertz, &Id);
if (RETURN_ERROR (Status)) {
return Status;
}
@@ -57,6 +75,32 @@ PlatformHookSerialPortInitialize (
return Status;
}
+ Status = PcdSet32S (PcdSerialRegisterStride, RegWidth);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialClockRate, InputHertz);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ SerialParam = PcdGetPtr(PcdPciSerialParameters);
+ SerialParam->VendorId = (UINT16)Id;
+ SerialParam->DeviceId = Id >> 16;
+ SerialParam->ClockRate = InputHertz;
+ SerialParam->RegisterStride = RegWidth;
+
return RETURN_SUCCESS;
}
diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
index e5db75f..87497f3 100644
--- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -19,6 +19,7 @@
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformHookLib
+ CONSTRUCTOR = PlatformHookSerialPortInitialize
[Sources]
PlatformHookLib.c
@@ -33,6 +34,10 @@
CorebootModulePkg/CorebootModulePkg.dec
[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
-
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES
--
1.9.1
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