Hi, Lee, OK, I see. Thank you for the explanation! The PCD can point to an array of PCI_SERIAL_PARAMETER structure. It makes sense.
Thanks Maurice -----Original Message----- From: Leahy, Leroy P Sent: Wednesday, April 20, 2016 10:38 AM To: Ma, Maurice Cc: [email protected]; Agyeman, Prince Subject: RE: [PATCH 07/12] CorebootPayloadPkg: Make serial I/O configurable Hi Maurice, This comment comes directly from MdeModulePkg\MdeModulePkg.dec line 1047. This PCD contains zero or more entries of the data structure. It is terminated when the VendorID value is 0xffff. Lee Leahy (425) 881-4919 Intel Corporation Suite 125 2700 - 156th Ave NE Bellevue, WA 98007-6554 -----Original Message----- From: Ma, Maurice Sent: Wednesday, April 20, 2016 10:25 AM To: Leahy, Leroy P <[email protected]> Cc: [email protected]; Agyeman, Prince <[email protected]> Subject: RE: [PATCH 07/12] CorebootPayloadPkg: Make serial I/O configurable Hi, Lee, The comment for the line below does not seem right. It is not a list at all. # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. Other than that it looks fine to me. Reviewed-by: Maurice Ma <[email protected]> Thanks Maurice -----Original Message----- From: Leahy, Leroy P Sent: Tuesday, April 19, 2016 1:31 PM To: [email protected]; Ma, Maurice; Agyeman, Prince; Leahy, Leroy P Subject: [PATCH 07/12] CorebootPayloadPkg: Make serial I/O configurable Allow the serial port configuration to be overriden from the command line. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <[email protected]> --- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 59 +++++++++++++++++++++++- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 58 ++++++++++++++++++++++- 2 files changed, 114 insertions(+), 3 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index d5f4fb1..df6f9c1 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -34,6 +34,40 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # Serial port set up + # + DEFINE BAUD_RATE = 115200 + DEFINE SERIAL_CLOCK_RATE = 1843200 + DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity + DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE + DEFINE SERIAL_DETECT_CABLE = FALSE + DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO + DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16 + DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE) + DEFINE UART_DEFAULT_DATA_BITS = 8 + DEFINE UART_DEFAULT_PARITY = 1 + DEFINE UART_DEFAULT_STOP_BITS = 1 + DEFINE DEFAULT_TERMINAL_TYPE = 0 + + # + # typedef struct { + # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. + # UINT16 DeviceId; ///< Device ID to match the PCI device + # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz + # UINT64 Offset; ///< The byte offset into to the BAR + # UINT8 BarIndex; ///< Which BAR to get the UART base address + # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. + # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT8 Reserved[2]; + # } PCI_SERIAL_PARAMETER; + # + # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride + = 1, Clock 1843200 (0x1c2000) # + # [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor] + DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} + + # # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI] # DEFINE SHELL_TYPE = FULL_BIN @@ -220,11 +254,32 @@ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 !else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - !endif + # + # The following parameters are set by Library/PlatformHookLib # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + + # + # Enable these parameters to be set on the command line # + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONT + ROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIA + L_HARDWARE_FLOW_CONTROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CA + BLE) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONT + ROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EX + TENDED_TX_FIFO_SIZE) + + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RA + TE) + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BI + TS) + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY) + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BI + TS) + + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYP + E) + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PAR + AMETERS) ################################################################################ # diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index db6c97d..67b70f0 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -34,6 +34,40 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # Serial port set up + # + DEFINE BAUD_RATE = 115200 + DEFINE SERIAL_CLOCK_RATE = 1843200 + DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity + DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE + DEFINE SERIAL_DETECT_CABLE = FALSE + DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO + DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16 + DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE) + DEFINE UART_DEFAULT_DATA_BITS = 8 + DEFINE UART_DEFAULT_PARITY = 1 + DEFINE UART_DEFAULT_STOP_BITS = 1 + DEFINE DEFAULT_TERMINAL_TYPE = 0 + + # + # typedef struct { + # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. + # UINT16 DeviceId; ///< Device ID to match the PCI device + # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz + # UINT64 Offset; ///< The byte offset into to the BAR + # UINT8 BarIndex; ///< Which BAR to get the UART base address + # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. + # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. + # UINT8 Reserved[2]; + # } PCI_SERIAL_PARAMETER; + # + # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride + = 1, Clock 1843200 (0x1c2000) # + # [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor] + DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} + + # # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI] # DEFINE SHELL_TYPE = FULL_BIN @@ -225,8 +259,30 @@ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F !endif + # + # The following parameters are set by Library/PlatformHookLib # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + + # + # Enable these parameters to be set on the command line # + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONT + ROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIA + L_HARDWARE_FLOW_CONTROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CA + BLE) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONT + ROL) + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EX + TENDED_TX_FIFO_SIZE) + + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RA + TE) + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BI + TS) + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY) + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BI + TS) + + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYP + E) + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PAR + AMETERS) ################################################################################ # -- 1.9.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
